參數(shù)資料
型號(hào): 28F200BX-TB
廠商: Intel Corp.
英文描述: 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
中文描述: 2兆位(128K的× 16,256K × 8)啟動(dòng)塊閃存系列
文件頁(yè)數(shù): 37/55頁(yè)
文件大?。?/td> 636K
代理商: 28F200BX-TB
E
4.6
2-MBIT SmartVoltage BOOT BLOCK FAMILY
37
SEE NEW DESIGN RECOMMENDATIONS
AC Characteristics
—WE#-Controlled Write Operations
(1)
—Commercial
Prod
BV-60
Sym
Parameter
V
CC
3.3 ± 0.3 V
(9)
5 V ± 5%
(10)
5 V ± 10%
(10)
Unit
Load
50 pF
30 pF
100 pF
Note
Min
Max
Min
Max
Min
Max
t
AVAV
Write Cycle Time
110
60
70
ns
t
PHWL
RP# Setup to WE# Going Low
0.8
0.45
0.45
μ
s
t
ELWL
CE# Setup to WE# Going Low
0
0
0
ns
t
PHHWH
Boot Block Lock Setup to WE#
Going High
V
PP
Setup to WE# Going High
6,8
200
100
100
ns
t
VPWH
5,8
200
100
100
ns
t
AVWH
Address Setup to WE# Going
High
3
90
50
50
ns
t
DVWH
Data Setup to WE# Going High
4
90
50
50
ns
t
WLWH
WE# Pulse Width
90
50
50
ns
t
WHDX
Data Hold Time from WE# High
4
0
0
0
ns
t
WHAX
Address Hold Time from WE#
High
3
0
0
0
ns
t
WHEH
CE# Hold Time from WE# High
0
0
0
ns
t
WHWL
WE# Pulse Width High
20
10
20
ns
t
WHQV1
Duration of Word/Byte Program
2,5
6
6
6
μs
t
WHQV2
Duration of Erase (Boot)
2,5,6
0.3
0.3
0.3
s
t
WHQV3
Duration of Erase (Parameter)
2,5
0.3
0.3
0.3
s
t
WHQV4
Duration of Erase (Main)
2,5
0.6
0.6
0.6
s
t
QVVL
V
PP
Hold from Valid SRD
5,8
0
0
0
ns
t
QVPH
RP# V
HH
Hold from Valid SRD
6,8
0
0
0
ns
t
PHBR
Boot-Block Lock Delay
7,8
200
100
100
ns
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