參數(shù)資料
型號(hào)： 28F200BX-B
廠商： Intel Corp.
英文描述： 5V or Adjustable, Low-Voltage, Step-Up DC-DC Controller
中文描述： 28F200BX - B組- 2兆位（128K的× 16。256K × 8）啟動(dòng)塊閃存系列
文件頁(yè)數(shù)： 20/55頁(yè)
文件大?。?/td> 636K
代理商： 28F200BX-B
2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
20
SEE NEW DESIGN RECOMMENDATIONS
Table 8. Status Register Bit Definition
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
(WSMS)
Check Write State Machine bit first to determine
Word/Byte program or Block Erase completion,
before checking Program or Erase Status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to
“1.” ESS bit remains set to “1” until an Erase
Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the
max number of erase pulses to the block and is
still unable to verify successful block erasure.
SR.4 = PROGRAM STATUS (DWS)
1 = Error in Byte/Word Program
0 = Successful Byte/Word Program
When this bit is set to “1,” WSM has attempted
but failed to program a byte or word.
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
Low Detect, Operation Abort
0 = V
PP
OK
The V
PP
Status bit does not provide continuous
indication of V
PP
level. The WSM interrogates V
PP
level only after the Program or Erase command
sequences have been entered, and informs the
system if V
PP
has not been switched on. The V
PP
Status bit is not guaranteed to report accurate
feedback between V
PPLK
and V
PPH
.
SR.2–SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use and should
be masked out when polling the status register.
3.3.2
STATUS REGISTER
The device status register indicates when a
program or erase operation is complete, and the
success or failure of that operation. To read the
status register write the Read Status (70H)
command to the CUI. This causes all subsequent
read operations to output data from the status
register until another command is written to the
CUI. To return to reading from the array, issue a
Read Array (FFH) command.
The status register bits are output on DQ
0
–DQ
7
, in
both byte-wide (x8) or word-wide (x16) mode. In the
word-wide mode the upper byte, DQ
8
–DQ
15
,
outputs 00H during a Read Status command. In the
byte-wide mode, DQ
8
–DQ
14
are tri-stated and
DQ
15
/A
–1
retains the low order address function.
Important:
The contents of the status register
are latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle.
This
prevents possible bus errors which might occur if
status register contents change while being read.
CE# or OE# must be toggled with each subsequent
status read, or the status register will not indicate
completion of a program or erase operation.
When the WSM is active, the SR.7 register will
indicate the status of the WSM, and will also hold
the bits indicating whether or not the WSM was
successful in performing the desired operation.
相關(guān)PDF資料
PDF描述
28F200BX-T Evaluation Kit for the MAX608
28F200BL-TB 2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
28F3204W30 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F200BX-T 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F200BX-T - 2-MBIT (128K x 16. 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
28F200BX-T/B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
28F200BX-TB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
28F200BX-TL/BL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
28F200CV-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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