參數(shù)資料
型號(hào): 28F160S3
廠商: Intel Corp.
英文描述: 3 V FlashFile Memory(3 V FlashFile 存儲(chǔ)器)
中文描述: 3伏FlashFile內(nèi)存(3伏FlashFile存儲(chǔ)器)
文件頁數(shù): 9/53頁
文件大?。?/td> 331K
代理商: 28F160S3
E
28F160S3/28F320S3
9
PRELIMINARY
56-LEAD SSOP
STANDARD PINOUT
16 mm x 23.7 mm
TOP VIEW
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
28FCE #
NC
A
20
A
19
A
18
A
17
A
16
V
CC
WE#
WP#
DQ
13
DQ
5
DQ
12
DQ
4
OE#
GND
DQ
6
DQ
14
DQ
7
DQ
15
A
12
A
13
A
14
A
15
3/5#
0
CE #
1
V
CC
STS
OE#
GND
A
8
BYTE#
NC
NC
GND
DQ
2
DQ
10
DQ
3
DQ
11
DQ
0
A
0
DQ
8
DQ
1
DQ
9
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
9
A
10
A
11
PP
R/P#
28F016SV
NC
WE#
WP#
DQ
13
DQ
5
DQ
12
DQ
4
GND
DQ
6
DQ
14
DQ
7
DQ
15
A
12
A
13
A
14
A
15
CE #
0
CE #
A
21
1
A
20
A
19
A
18
A
17
A
16
V
CC
V
CC
NC
NC
A
20
A
19
A
18
A
17
A
16
V
CC
WE#
WP#
DQ
13
DQ
5
DQ
12
DQ
4
OE#
GND
DQ
6
DQ
14
DQ
7
DQ
15
STS
A
12
A
13
A
14
A
15
CE #
0
CE #
1
V
CC
2V
PP
R/P#
GND
A
8
BYTE#
NC
NC
GND
DQ
2
DQ
10
DQ
3
DQ
11
DQ
0
A
0
DQ
8
DQ
1
DQ
9
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
9
A
10
A
11
28F016SV
GND
A
8
BYTE#
NC
NC
GND
DQ
2
DQ
10
DQ
3
DQ
11
DQ
0
A
0
DQ
8
DQ
1
DQ
9
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
9
A
10
A
11
PP
R/P#
RY/BY#
Hghlights pinout changes.
28F320S5
28F320S3
28F160S5
28F160S3
2V
28F320S3
2V
28F160S3
0608_03
Figure 3. SSOP 56-Lead Pinout
2.0
PRINCIPLES OF OPERATION
The 3 Volt memories include an on-chip Write
State Machine (WSM) to manage block erase,
program, and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed
power
supplies
during
programming, lock-bit configuration, and minimal
processor overhead with RAM-like interface
timings.
block
erasure,
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation
of external memory control pins allow array read,
standby, and output disable operations.
Read array, status register, query, and identifier
codes can be accessed through the CUI
independent
of
the
V
PP
voltage.
Proper
programming voltage on V
PP
enables successful
block
erasure,
program,
configuration. All functions associated with
altering memory contents
—block erase, program,
lock-bit configuration—are accessed via the CUI
and verified through the status register.
and
lock-bit
Commands are written using standard micro-
processor write timings. The CUI contents serve
as input to the WSM that controls the block
erase, programming, and lock-bit configuration.
The internal algorithms are regulated by the
WSM,
including
pulse
verification, and margining of data. Addresses
and data are internally latched during write
cycles. Writing the appropriate command outputs
array data, identifier codes, or status register
data.
repetition,
internal
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