E
1.0
28F160S3/28F320S3
5
PRELIMINARY
INTRODUCTION
This datasheet contains 16- and 32-Mbit 3 Volt
FlashFile
TM
memory (28F160S3 and 28F320S3)
specifications. Section 1.0 provides a flash memory
overview. Sections 2.0 through 5.0 describe the
memory organization and functionality. Section 6.0
covers
electrical
specifications
temperature product offerings. Finally, Section 7.0
provides ordering and reference information.
for
extended
1.1
New Features
The 3 Volt FlashFile memory family maintains basic
compatibility with Intel’s 28F016SA and 28F016SV.
Key enhancements include:
Common Flash Interface (CFI) Support
Scaleable Command Set (SCS) Support
Low Voltage Technology
Enhanced Suspend Capabilities
They share a compatible status register, basic
software commands, and pinout. These similarities
enable a clean migration from the 28F016SA or
28F016SV. When upgrading, it is important to note
the following differences:
Because of new feature and density options,
the devices have different manufacturer and
device identifier codes. This allows for software
optimization.
New software commands.
To take advantage of low voltage on the
28F160S3
and
28F320S3,
connection to V
CC
. The 28F160S3 and
28F320S3 do not support a 12 V V
PP
option.
allow
V
PP
1.2
Product Overview
The 3 Volt FlashFile memory family provides
density upgrades with pinout compatibility for the
16- and 32-Mbit densities. They are high-
performance memories arranged as 1 Mword and
2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of
8 bits. This data is grouped in thirty-two and sixty-
four 64-Kbyte blocks that can be erased, locked
and unlocked in-system. Figure 1 shows the block
diagram, and Figure 4 illustrates the memory
organization.
This family of products are optimized for fast factory
programming and low power designs. Specifically
designed for 3 V systems, the 28F160S3 and
28F320S3 support read operations at 2.7 V–3.6 V
V
CC
with block erase and program operations at
2.7 V–3.6 V and 5 V V
PP
. High programming
performance is achieved through highly-optimized
write buffers. A 5 V V
PP
option is available for even
faster factory programming. For a simple low power
design, V
CC
and V
PP
can be tied to 2.7 V.
Additionally, the dedicated V
PP
pin gives complete
data protection when V
PP
≤
V
PPLK
.
Internal V
PP
detection circuitry
configures
the
operations.
automatically
optimized
device
for
write
A Common Flash Interface (CFI) permits OEM-
specified software algorithms to be used for entire
families of devices. This allows device-independent,
JEDEC
ID-independent,
backward-compatible software support for the
specified flash device families. Flash vendors can
standardize their existing interfaces for long-term
compatibility.
and
forward-
and
Scaleable Command Set (SCS) allows a single,
simple software driver in all host systems to work
with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement).
Additionally,
SCS
provides
system/device data transfer rates and minimizes
device and system-level implementation costs.
the
highest
A Command User Interface (CUI) serves as the
interface between the system processor and
internal device operation. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within t
WHQV2/EHQV2
independent of other blocks. Each block can be
independently erased 100,000 times in the
commercial temperature range (0 °C to +70 °C) and
10,000 times in the extended temperature range
(–40 °C to +85 °C). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
Data is programmed in byte, word or page
increments. Program suspend mode enables the