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參數(shù)資料
| 型號： | 28F160S3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 V FlashFile Memory(3 V FlashFile 存儲器) |
| 中文描述： | 3伏FlashFile內(nèi)存（3伏FlashFile存儲器） |
| 文件頁數(shù)： | 11/53頁 |
| 文件大?。?/td> | 331K |
| 代理商： | 28F160S3 |
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E
3.1
28F160S3/28F320S3
11
PRELIMINARY
Read
Block information, query information, identifier
codes and status registers can be read
independent of the V
PP
voltage.
The first task is to place the device into the
desired read mode by writing the appropriate
read-mode command (Read Array, Query, Read
Identifier Codes, or Read Status Register) to the
CUI. Upon initial device power-up or after exit
from deep power-down mode, the device
automatically resets to read array mode. Control
pins dictate the data flow in and out of the
component. CE
#, CE
1
# and OE# must be driven
active to obtain data at the outputs. CE
0
# and
CE
1
# are the device selection controls, and,
when both are active, enable the selected
memory device. OE# is the data output (DQ
0
–
DQ
15
) control: When active it drives the selected
memory data onto the I/O bus. WE# must be at
V
and RP# must be at V
IH
. Figure 17 illustrates
a read cycle.
3.2
Output Disable
With OE# at a logic-high level (V
), the device
outputs are disabled. Output pins DQ
0
–DQ
15
are
placed in a high-impedance state.
3.3
Standby
CE
0
# or CE
1
# at a logic-high level (V
) places
the device in standby mode, substantially
reducing device power consumption. DQ
0
–DQ
15
(or DQ
0
– DQ
7
in x8 mode) outputs are placed in
a high-impedance state independent of OE#. If
deselected during block erase, programming, or
lock-bit configuration, the device continues
functioning and consuming active power until the
operation completes.
3.4
Deep Power-Down
RP# at V
IL
initiates the deep power-down mode.
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be
held low for time t
PLPH
. Time t
PHQV
is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI
resets to read array mode, and the status register
is set to 80H.
During block erase, programming, or lock-bit
configuration modes, RP#-low will abort the
operation. STS in RY/BY# mode remains low
until the reset operation is complete. Memory
contents being altered are no longer valid; the
data
may
be
partially
programming or partially altered after an erase or
lock-bit configuration. Time t
PHWL
is required after
RP# goes to logic-high (V
IH
) before another
command can be written.
corrupted
after
It is important in any automated system to assert
RP# during system reset. When the system
comes out of reset, it expects to read from the
flash memory. Automated flash memories
provide status information when accessed during
block
erase,
programming,
configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization
may not occur because the flash memory may be
providing status information instead of array data.
Intel’s Flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that
resets the system CPU.
or
lock-bit
3.5
Read Query Operation
The read query operation outputs block status,
Common Flash Interface (CFI) ID string, system
interface, device geometry, and Intel-specific
extended query information.
3.6
Read Identifier Codes
Operation
The read-identifier codes operation outputs the
manufacturer code, device code, and block lock
configuration codes for each block configuration
(see Figure 5). Using the manufacturer and
device
codes,
the
system
automatically match the device with its proper
algorithms. The block-lock configuration codes
identify each block’s lock-bit setting.
software
can
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