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參數(shù)資料
| 型號： | 24919 |
| 英文描述： | Incompatibilities Between the AMD-762? System Controller and the Via Technologies. Inc. VT82C686B |
| 中文描述： | 不相容了AMD - 762？系統(tǒng)控制器和威盛。公司VT82C686B |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 65K |
| 代理商： | 24919 |
5
24919B
—
June 2001
Incompatibilities Between the AMD-762
System Controller and the Via Technologies, Inc. VT82C686B
“
Super South
”
Southbridge
Confidential - Advance Information
The AMD-762 system controller supports the ACPI S3 state by
specific sequencing on the DCSTOP# and PCIR E SE T# pins.
When entering the S3 state the DCSTOP# pin must be asserted
followed by the assertion of the PCIRE SET# pin one RTC clock
later (~30 mS). The PCIR E SE T # assertion is used by the
AMD-762 system controller to gate off its I/O pad ring since the
pad ring will be powered off while the core remains powered
(the DDR I/O pad ring remains powered). Approximately four
clocks later the DDR clocks will be disabled. Since registered
DIMMs incorporate PL L s and registers on the module, they
require a separate reset pin that must be asserted before its
clocks are removed to guarantee stable operation.
A s shown in Figure 2 on page 4, the reset pin on the DDR
DIMMs is connected to the Southbridge
’
s PCIRE SE T# pin in a
AMD-762 system controller based system. When entering the
Suspend to R A M state, the A MD-762 system controller will
continue to drive the DDR clocks for at least four clocks after
the PCIRST# pin is asserted to meet the DIMM requirements.
I
The V T82C686B does not follow the DCSTOP# and
PCIRESET# sequencing listed above. The V T82C686B does
not assert the PCIRESET# pin low until after the power
supply is turned off (PWRGOOD de-asserted). This means
that the system clock generator is powered off by the time
the AMD-762 system controller detects the assertion of
PCIRESE T#. This potentially results in DDR memory
failures since the DIMM was not properly shut down.
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相關(guān)代理商/技術(shù)參數(shù) |
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