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| 型號(hào)： | 24945 |
| 英文描述： | Implementing SDLC on the Am186CC or Am186CH Microcontroller Application Note? 76.1KB (PDF) |
| 中文描述： | 實(shí)施的SDLC的Am186CC或Am186CH微控制器應(yīng)用筆記？ 76.1KB（PDF格式） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 76K |
| 代理商： | 24945 |
Publication#
24945
Issue Date:
April 2001
Rev:
A
Amendment/
0
Copyright 2001 Advanced Micro Devices, Inc. All rights reserved.
Implementing SDLC on the Am186CC or
Am186CH Microcontroller
Application Note
by Erwin Han
SDLC is a layer 2 communication protocol similar to the HDLC protocol. The Am186CC and
Am186CH microcontrollers support SDLC bit manipulation via their address match and address
mask registers. An SDLC environment might use any of several encoding methods. Whether these
microcontrollers can be used in an SDLC environment depends on the encoding method used.
OVERVIEW
This application note describes the difference between
High-level Data Link Control (HDLC) and Synchronous
Data Link Control (SDLC), and various methods of en-
coding used in serial communication. It points out de-
sign considerations for using the Am186CC or
Am186CH microcontroller in an SDLC system.
BIT MANIPULATION
The following sections introduce basic concepts of
HDLC and related protocols, describe the difference
between HDLC and SDLC, and explain SDLC address-
ing considerations.
Introduction to HDLC
In the 7-layer Open System Interconnection (OSI)
model, layer 2 is the data link layer. This layer provides
control between physical nodes: link initialization, flow
control, and error control. One of the most common
layer 2 protocols is HDLC. In HDLC, all transmissions
are in frames. Actually, many other common layer 2
protocols are based on the framing structure of HDLC,
like SDLC, LAPB, LAPD, etc. Figure 1 shows the frame
structure of HDLC.
Flag
The flag field is defined as 7Eh (hexadecimal), which is
01111110b (binary) in serial transmission.
Zero Insertion
HDLC uses a zero insertion/deletion scheme (inserting
a 0 bit after five continuous 1 bits when transmitting,
then deleting the added bits when receiving) to ensure
that the flag bit pattern (01111110) does not occur in the
fields between flags.
Address
Because the layer 2 (data link layer) frame can be
transmitted over a point-to-point link, a broadcast net-
work, or packet switched systems, there is an address
field in the frame to carry the frame’s destination ad-
dress. The length of this field is commonly 0, 8, or 16
bits for the “HDLC family” protocols, depending on the
layer 2 protocol. For instance, HDLC and LAPD use a
16-bit address; SDLC and LAPB use an 8-bit address.
Control
The 8- or 16-bit control field provides a flow control
number and defines the frame type (control or data).
The exact length and use of this field depends on the
protocol.
Information/Data
Data is transmitted in the information field, which can
vary in length depending on the protocol. Layer 3
frames are carried in this information field.
Error Control
Error control is implemented by appending a Cyclic Re-
dundancy Check (CRC) to the frame. All data transmit-
ted between the opening and closing flags (excluding
inserted 0s) are included in the CRC calculation. The
calculated CRC is appended to the end of the frame
just before the closing flag. The CRC field is 16-bits
long in most protocols, but may be 32-bits long in some
protocols.
Order of Transmitting
In HDLC and SDLC, the least-significant bit (LSB) of
each data octet is transmitted first, and the most-signif-
icant bit (MSB) of the CRC is transmitted first.
Figure 1.
HDLC Frame Structure
Opening Flag
8 bits
Address
16 bits
Control
8/16 bits
Information (Optional)
8N bits (N=0,1,2…)
CRC
16 bits
Closing Flag
8 bits
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