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| 型號(hào)： | 24945 |
| 英文描述： | Implementing SDLC on the Am186CC or Am186CH Microcontroller Application Note? 76.1KB (PDF) |
| 中文描述： | 實(shí)施的SDLC的Am186CC或Am186CH微控制器應(yīng)用筆記？ 76.1KB（PDF格式） |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 76K |
| 代理商： | 24945 |
3
Implementing SDLC on the Am186CC or Am186CH Microcontroller
8-Bit Address Recognition Example
To accept a frame that begins with 7Eh (flag) and 5Bh,
using 8-bit address recognition, the low byte of one
HxA0–HxA3 register should contain 5Bh, and the cor-
responding HxAnMSK should contain 00FFh.
The configuration shown in Figure 3 recognizes:
I
One 8-bit address: 5B
I
A set of 8-bit address: 50–5F
Figure 3.
8-Bit Address Matching Example
Note:
If one of the HxA0–HxA3 registers contains
xx5Bh, and the corresponding HxAnMSK contains
00FFh, the HDLC controller accepts any frame starting
with 7E (Flag), 5Bh. This might be either a 16-bit ad-
dress xx5Bh or an 8-bit address 5Bh. Because the con-
tent of the frame (starting from the byte after Flag) is
saved in the receiving buffer, the programmer will know
whether to handle it as 16-bit address or 8-bit address.
Control
In some SDLC controllers, there is logic to automati-
cally handle certain types of frames, as defined by the
bits in the control field. The HDLC controllers in the
Am186CC and Am186CH microcontrollers do not sup-
port automatic handling; it must be done by software.
ENCODING
In serial communication, there are many ways to en-
code the data, such as NRZ, NRZI, FM0, FM1,
Manchester, etc. Examples of some different encoding
methods are shown in Figure 4.
NRZ (Non-Return to Zero)
In NRZ encoding, a 1 bit is represented by a High level
and a 0 bit is represented by a Low level. In this encod-
ing method, only a minimal amount of clocking informa-
tion is available in the data stream in the form of
transitions on bit-cell boundaries. In an arbitrary data
pattern, this may not be sufficient to generate a clock
for the data from the data itself.
NRZI (Non-Return to Zero Inverted)
In NRZI encoding, a 1 bit is represented by no change in
the level, and a 0 bit is represented by a change in the
level. As in NRZ, only a minimal amount of clocking in-
formation is available in the data stream, in the form of
transitions on bit cell boundaries. In an arbitrary data
pattern, this may not be sufficient to generate a clock for
the data from the data itself. In the case of HDLC/SDLC
mode, where the number of consecutive 1 bits in the
data stream is limited (by zero insertion), a minimum
number of transitions to generate a clock is provided.
Figure 4.
Data Encoding
Frame with 8-bit Address
Address
5B
Flag
7E
Control
AC
Etc.
Match and Mask Register Contents
HxA0 xx5B
HxA0MSK 00FF
HxA1 xx5x
HxA1MSK 00F0
HxA2 xxxx
HxA2MSK 0000
HxA3 xxxx
HxA3MSK 0000
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