
Implementing SDLC on the Am186CC or Am186CH Microcontroller
4
FM0 (Biphase Space)
In FM0 encoding, also known as biphase space, a tran-
sition is present on every bit cell boundary, and an ad-
ditional transition may be present in the middle of the
bit cell. In FM0, a 1 bit is sent as no transition in the cen-
ter of the bit cell, and a 0 bit is sent as a transition in the
center of the bit cell. FM0 encoding data contains suffi-
cient information to recover a clock from the data.
FM1 (Biphase Mark)
In FM1 encoding, also known as biphase mark, a tran-
sition is present on every bit cell boundary, and an ad-
ditional transition may be present in the middle of the
bit cell. In FM1, a 0 bit is sent as no transition in the cen-
ter of the bit cell, and a 1 bit is sent as a transition in the
center of the bit cell. FM1 encoded data contains suffi-
cient information to recover a clock from the data.
Manchester
Manchester encoding always produces a transition at
the center of the bit cell. If the transition is High-to-Low,
the bit is a 1; if the transition is Low-to-High, the bit is a
0. Manchester encoded data contains sufficient infor-
mation to recover a clock from the data. Manchester
encoding is used in 10-Mbit/s Ethernet.
Digital Phase-Locked Loop (DPLL)
Many communication controllers (like the Am85C30,
MC68360, and all 10 Mbit/s Ethernet controllers) have
a DPLL that can be used to recover clock information
from a data stream with NRZI, FM or Manchester en-
coding. The data stream encoded in these ways con-
tains sufficient information to recover a clock from the
data.
Advantage and Drawback
The advantage of encoding mechanisms that include
sufficient clock information (e.g., NRZI, FM, and
Manchester) is that clock information can be recovered
from the data stream so a separate clock is not needed.
Therefore, the number of wires for transmission is min-
imized. However, FM and Manchester encoding have a
drawback in that the worst-case signaling rate is twice
the data rate.
Encodings Supported by the Am186CC and
Am186CH Microcontrollers
The Am186CC and Am186CH microcontrollers sup-
port NRZ and NRZI encoding. They do not support
FM0, FM1, and Manchester encoding. These micro-
controllers do not have a DPLL, therefore they cannot
recover clock information from an NRZI data stream.
When NRZI is used and there is no separate clock ac-
companying the data stream, these microcontrollers
need an external DPLL to retrieve a clock signal from
the received data. This clock will be used for both re-
ceiving and transmitting.
SUMMARY
The HDLC controller in the Am186CC and Am186CH
microcontrollers supports all the bit manipulation of the
SDLC protocol. Whether or not these microcontrollers
can be used in an SDLC environment depends on what
method of encoding is used.
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Table 2.
Encoding Support
Encoding Method
Supported by Am186CC and
Am186CH Microcontrollers
NRZ
Yes
NRZI with separate
clock
Yes
NRZI without
separate clock
Yes, but only with external DPLL
FM0 or FM1
No
Manchester
No