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參數(shù)資料
| 型號： | 24919 |
| 英文描述： | Incompatibilities Between the AMD-762? System Controller and the Via Technologies. Inc. VT82C686B |
| 中文描述： | 不相容了AMD - 762？系統(tǒng)控制器和威盛。公司VT82C686B |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 65K |
| 代理商： | 24919 |
4
Incompatibilities Between the AMD-762
TM
System Controller and the Via Technologies, Inc. VT82C686B
“
Super South
”
Southbridge
24919B
—
June 2001
Confidential - Advance Information
indicate that the Southbridge
’
s IOAPIC can issue an
interrupt message to the local APIC. The AMD-762 system
controller will not assert the WSC# pin low unless it first
receives a request on this pin.
The V T82C686B implements WSC# as a unidirectional pin
that is only driven by the Northbridge and must be asserted
low unless the Northbridge has outstanding PCI to DRAM
posted writes that have not been snooped by the processor.
When the V T82C686B is connected to an AMD-762 system
controller the WSC# pin will never be asserted because the
V T82C686B does not first assert WSC# to request posted
writes to be snooped, and thus the system will not be able to
send interrupt messages to the processor.
I
ACPI S3 Incompatibility with Registered DDR DIMMs
Systems employing registered DDR DIMMs and the AMD-762
system controller/V T82C686B combination may experience
data corruption when entering or exiting the ACPI S3 (Suspend
to R A M) power management state. T his is due to an
incompatibility in the sequencing of the PCIR E SE T# signal
between the Northbridge and the Southbridge.
Figure 2.
DDR DIMM Reset Connection in AMD-762 System Controller System
CPU
AMD-762
TM
System
Controller
Southbridge
PCIRESET#
STPCLK#
Registered
DDR DIMMs
CLK
D
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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