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| 型號(hào)： | 24919 |
| 英文描述： | Incompatibilities Between the AMD-762? System Controller and the Via Technologies. Inc. VT82C686B |
| 中文描述： | 不相容了AMD - 762？系統(tǒng)控制器和威盛。公司VT82C686B |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 65K |
| 代理商： | 24919 |
3
24919B
—
June 2001
Incompatibilities Between the AMD-762
System Controller and the Via Technologies, Inc. VT82C686B
“
Super South
”
Southbridge
Confidential - Advance Information
Figure 1.
IOAPIC vs. Traditional PIC System Configuration
The mechanism typically employed in chipsets to flush the
posted write-buffers is a simple protocol between the
Northbridge and the Southbridge that signals the completion
of processor snooping of all posted write-buffers, indicating
that an interrupt message may be safely sent from the IOAPIC
to the local APIC. This mechanism is known as
“
Write Snoop
Complete
”
and is implemented with a pin called
“
WSC#. The
WSC# pin is supported on both the AMD-762 system controller
and the V T82C686B Southbridge, but the implementations are
functionally incompatible as follows:
I
The AMD-762 system controller implements WSC# as a
bidirectional pin that is first asserted by the Southbridge to
request that the posted write-buffers be snooped by the
processor, and subsequently asserted by the Northbridge to
IOAPIC
I
nterrupt
Message Bus
3
CPU
Northbridge
Southbridge
PIC
INTR
CPU
Northbridge
Southbridge
Interrupt
Acknowledge Cycle
on PCI Bus
WSC#
IOAPIC System Configuration
Peripheral interrupt request occurs, IOAPIC must send
interrupt message to the processor.
WSC# protocol forces Northbridge and CPU to snoop
all posted writes, and provide a status indicator to the
Southbridge
Southbridge/IOAPIC is now free to issue message to
CPU on the interrupt bus
Processor reads of memory are coherent.
PIC System Configuration
Peripheral interrupt request occurs, PIC sends inter-
rupt request to the processor on the INTR pin.
Processor responds with interrupt acknowledge cycle
Interrupt acknowledge cycle forces Northbridge to
flush all posted writes
Processor reads of memory are coherent.
1.
2.
3.
4.
Posted Writes
Posted Writes
Snoop
Snoop
1.
2.
3.
4.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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