參數(shù)資料
型號: 24919
英文描述: Incompatibilities Between the AMD-762? System Controller and the Via Technologies. Inc. VT82C686B
中文描述: 不相容了AMD - 762?系統(tǒng)控制器和威盛。公司VT82C686B
文件頁數(shù): 6/10頁
文件大?。?/td> 65K
代理商: 24919
2
Incompatibilities Between the AMD-762
TM
System Controller and the Via Technologies, Inc. VT82C686B
Super South
Southbridge
24919B
June 2001
Confidential - Advance Information
Write Snoop Protocol
Incompatibilty
The Microsoft
Windows
Logo Program R equirements 2.0
v.0.9
requires that all desktop systems must be A dvanced
Programmable Interrupt Controller (A PIC) enabled (SY S-
001.3). This requires that all hardware interrupts be connected
to the IOA PIC, and that the IOA PIC be connected to the
processor
s local A PIC. The communication between the
IOAPIC and the local APIC occurs over a separate sideband
bus. A comparison of this configuration to the traditional PIC
configuration is shown in Figure 1 on page 3.
Operation with the IOAPIC and the local APIC requires all of
the Northbridge
s posted write-buffers to be properly flushed
to coherent memory before the IOA PIC sends an interrupt
message to the processor. This is required to prevent potential
data coherency problems that may result when the processor
receives an interrupt and reads stale data because the data
most recently written by the PCI Bus master still resides in a
posted wri te-buffer in the Northbridge. Non-A P IC
implementations do not have the potential for this problem
because the processor
s interrupt acknowledge cycle that
traverses the PCI Bus is serializing in nature, thus all posted-
write buffers are flushed before the processor reads memory in
the interrupt service routine.
Note:
The solution using a POP/NOPOP resistor for single
processor
configurations
application note, Interfacing the AMD-761
TM
system
controller
and
the
Via
Southbridge, does not apply to multiprocessor solutions
using the AMD-762 system controller.
published
in
the
24952A
Technologies
VT62C686B
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