54
Model D Registers
Embedded AMD-K6 Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Enhanced Power Management Register (EPMR) (Low-Power Versions)
To support AMD PowerNow! technology, the low-power versions
of the AMD-K6-2E+ and AMD-K6-IIIE+ processors Model D are
designed with enhanced power management (EPM) features:
dynamic bus divisor control, and dynamic voltage ID control.
The EPMR register (see Figure 26) defines the base address for
a 16-byte block of I/O address space. Enabling the EPMR allows
software to access the EPM 16-byte I/O block, which contains
bits for enabling, controlling, and monitoring the EPM features.
Table 25 defines the functions of each bit in the EPMR register.
The EPMR register is MSR C000_0086h.
Figure 26. Enhanced Power Management Register (EPMR) (Low-Power Model D)
Table 25. Enhanced Power Management Register (EPMR) Definition (Low-Power Model D)
Bit
Description
R/W
Function
1
All reserved bits are always read as 0.
IOBASE defines a base address for a 16-byte block of I/O
address space accessible for enabling, controlling, and monitor-
ing the EPM features.
All reserved bits are always read as 0.
This bit controls whether a special bus cycle is generated upon
dword accesses within the EPM 16-byte block. If set to 1, an
EPM special bus cycle is generated, where BE[7:0]# = BFh and
A[4:3] = 00b.
This bit controls access to the mapped I/O address space for
the EPM features. Clearing this bit does not affect the state of
bits defined in the EPM 16-byte I/O block.
Notes:
1.
All bits default to 0 when RESET is asserted.
63–16
Reserved
R
15-4
I/O BASE Address (IOBASE)
R/W
3-2
Reserved
R
1
Generate Special Bus Cycle (GSBC)
R/W
0
Enable AMD PowerNow! Technology
Management (EN)
R/W
C
M
D
Reserved
Description
I/O Base Address
Generate Special Bus Cycle
Enable AMD PowerNow! Technology
Management
0
16
63
15
4
3
1
2
E
N
G
S
B
C
IOBASE
Symbol
IOBASE
GSBC
EN
Bit
15-4
1
0