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參數(shù)資料
| 型號(hào)： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁(yè)數(shù)： | 42/98頁(yè) |
| 文件大?。?/td> | 1365K |
| 代理商： | 23913A |
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Model 8/[F:8] Registers
Embedded AMD-K6 Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
UC/WC Cacheability Control Register (UWCCR)
Models 8/[F:8], 9, and D provide two variable-range Memory
Type Range Registers (MTRRs)—MTRR0 and MTRR1—that
each specify a range of memory. Each range can be defined as
one of the following memory types:
I
Uncacheable (UC) Memory
—Memory read cycles are sourced
directly from the specified memory address, and the
processor does not allocate a cache line. Memory write
cycles are targeted at the specified memory address, and a
write allocation does not occur.
Write-Combining (WC) Memory
—Memory read cycles are
sourced directly from the specified memory address, and the
processor does not allocate a cache line. The processor
conditionally combines data from multiple noncacheable
write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single
write cycle reduces processor bus utilization and processor
stalls, thereby increasing the overall system performance.
This memory type is applicable for linear video frame
buffers.
Note:
The MTRRs defined in this document are not software-
compatible to the MTRRs defined by the Pentium Pro and
Pentium II processors.
I
The programmer accesses the MTRRs by addressing the 64-bit
MSR known as the UC/WC Cacheability Control Register
(UWCCR). The MSR address of the UWCCR is C000_0085h.
Following reset, all bits in the UWCCR register are set to 0.
MTRR0 (lower 32 bits of the UWCCR register) defines the size
and memory type of range 0 and MTRR1 (upper 32 bits) defines
the size and memory type of range 1 (see Figure 7 on page 31).
Prior to programming write-combining or uncacheable areas of
memory in the UWCCR, the software must disable the
processor’s cache, then flush the cache. This can be achieved by
setting the CD bit in CR0 to 1 and executing the WBINVD
instruction. Following the programming of the UWCCR, the
processor’s cache must be enabled by setting the CD bit in CR0
to 0.
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