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| 型號： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計(jì)指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁數(shù)： | 39/98頁 |
| 文件大?。?/td> | 1365K |
| 代理商： | 23913A |
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Model 8/[F:8] Registers
27
23913A/0—November 2000
Embedded AMD-K6 Processors BIOS Design Guide
Preliminary Information
Write Handling Control Register (WHCR)
The Write Handling Control Register (WHCR) (see Figure 6 on
page 28) is an MSR that contains two fields—the Write Allocate
Enable Limit (WAELIM) field and the Write Allocate Enable
15-to-16-Mbyte (WAE15M) bit. The WHCR register is MSR
C000_0082h.
Note:
The WHCR register as defined in the models 7 and 8/[7:0] is
defined differently in models 8/[F:8], 9, and D. A complete
description of the newly defined register is included in this
section for models 8/[F:8], 9, and D.
AMD-K6 processors contain a split level-1 (L1) 64-Kbyte
writeback cache organized as a separate 32-Kbyte instruction
cache and a 32-Kbyte data cache with two-way set associativity.
The cache line size is 32 bytes, and lines are read from memory
using an efficient pipelined burst read cycle. Further
performance gains are achieved by the implementation of a
write allocation scheme.
Write Allocation
A write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the L1 cache. For more information
on write allocate, see the
Implementation of Write Allocate in the
K86 Processors Application Note
, order# 21326 and see the
“Cache Organization” chapter in the appropriate AMD-K6 or
AMD-K6E processor data sheet.
This section describes two programmable mechanisms used by
the processor to determine when to perform write allocate.
When either of these mechanisms indicates that a pending
write is to a cacheable area of memory, a write allocate is
performed.
Before enabling write allocate or changing memory
cacheability, the BIOS must write back and invalidate the
internal cache by using the WBINVD instruction. In addition,
write allocate should be enabled only after performing any
memory sizing or typing algorithms.
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