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參數(shù)資料
| 型號： | 23913A |
| 英文描述： | Embedded AMD-K6 Processors BIOS Design Guide Application Note? 1.33MB (PDF) |
| 中文描述： | 嵌入式的AMD - K6處理器的BIOS設(shè)計指南應(yīng)用筆記？ 1.33MB（PDF格式） |
| 文件頁數(shù)： | 52/98頁 |
| 文件大?。?/td> | 1365K |
| 代理商： | 23913A |
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40
Model 9 Registers
Embedded AMD-K6 Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Level-2 Cache Array Access Register (L2AAR)
Models 9 and D provide the L2AAR register that allows for
direct access to the L2 cache and L2 tag arrays. The L2 cache in
the AMD-K6-III processor is organized as shown in Figure 11:
I
Four 64-Kbyte ways
Each way contains 1024 sets
Each set contains four 64-byte sectors (one sector in each
way)
Each sector contains two 32-byte cache lines
Each cache line contains four 8-byte octets
Each octet contains an upper and lower dword (4 bytes)
I
I
I
I
I
Each line within a sector contains its own MESI state bits, and
associated with each sector is a tag and least recently used
(LRU) information.
Figure 11. L2 Cache Organization (AMD-K6
-III
Processor)
The L2AAR register is MSR C000_0089h.
The operation that is performed on the L2 cache is a function of
the instruction executed—RDMSR or WRMSR—and the
contents of the EDX register. The EDX register specifies the
location of the access, and whether the access is to the L2 cache
data or tags (see Figure 13 on page 41).
Figure 12 on page 41 shows the L2 cache sector and line
organization. If bit 5 (see Figure 13) of the address of a cache
line equals 1, then this cache line is stored in Line 1 of a sector.
Similarly, if bit 5 of the address of a cache line equals 0, then
this cache line is stored in Line 0 of a sector.
1
Set 0
64 bytes
Way 2
Line1/MESI
Line0/MESI
Tag/LRU
64 bytes
Way 1
Line1/MESI
Line0/MESI
Tag/LRU
64 bytes
Way 0
Line1/MESI
Line0/MESI
Tag/LRU
64 bytes
Way 3
Line1/MESI
Line0/MESI
Tag/LRU
Set 1023
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