參數(shù)資料
型號(hào)： 21041
廠商： Intel Corp.
英文描述： Digital Semiconductor 21041 PCI Ethernet LAN Controller(數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)LAN控制器)
中文描述： 數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)局域網(wǎng)控制器（數(shù)字半導(dǎo)體21041的PCI以太網(wǎng)局域網(wǎng)控制器）
文件頁數(shù)： 9/64頁
文件大?。?/td> 230K
代理商： 21041
1 Digital Semiconductor 21041 Overview
The Digital Semiconductor 21041 PCI Ethernet LAN Controller (21041)
provides a direct interface connection to the peripheral component interconnect
(PCI) bus and adapts easily to most other standard buses. The 21041 provides
a direct Ethernet connection to the twisted-pair (TP) interface and attachment
unit interface (AUI).
The 21041 operates in two modes: mode 0 and mode 1. In mode 0 operation,
the 21041 is software compatible with the 21040 and functions as a 21040. In
mode 1 operation, the 21041 incorporates enhanced features that are described
in this document. For a description of mode 0 operation, refer to the
DECchip
21040 Ethernet LAN Controller for PCI Data Sheet
and the
DECchip 21040
Ethernet LAN Controller for PCI Hardware Reference Manual
.
1.1 General Description
The 21041 interfaces with the PCI using onchip control and status registers
(CSRs), and a shared system memory area that is set up mainly during
initialization. This minimizes the CPU involvement in the 21041 operation
during normal reception and transmission. The 21041 is compliant with the
PCI Local Bus Specification, Revision 2.0
and the
PCI Local Bus Specification,
Revision 2.1
. Bus traffic is also minimized by filtering out received runt frames
and by automatically retransmitting collided frames without needing to repeat
a fetch from system memory.
The 21041 provides a direct interface to a 64KB, 128KB, or 256KB boot
ROM. It supports both PCI 3.3-volt and 5.0-volt signaling environments and a
power-down mode for energy conservation.
On the network side, the 21041 provides an AUI and a TP interface, enabling
a low chip count connection to the two most popular Ethernet interfaces. The
21041 can sustain transmission or reception of minimal-sized, back-to-back
packets at full line speed with an interpacket gap (IPG) of 9.6 microseconds.
It is also capable of functioning in a full-duplex environment, and it supports
IEEE 802.3 autonegotiation algorithm of full-duplex and half-duplex network
environments.
1
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