參數(shù)資料
型號(hào): 21041
廠商: Intel Corp.
英文描述: Digital Semiconductor 21041 PCI Ethernet LAN Controller(數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)LAN控制器)
中文描述: 數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)局域網(wǎng)控制器(數(shù)字半導(dǎo)體21041的PCI以太網(wǎng)局域網(wǎng)控制器)
文件頁(yè)數(shù): 19/64頁(yè)
文件大?。?/td> 230K
代理商: 21041
Table 4 Quick Pin Reference
Signal
Type
Pin
Number
Description
ad<31:00>
I/O
See
Figure 2.
32-bit multiplexed PCI address and data lines.
Address and data bits are multiplexed on the
same pins. During the first clock cycle of a
transaction,
ad<31:00>
contain a physical
byte address (32 bits). During subsequent
clock cycles,
ad<31:00>
contain data. A 21041
bus transaction consists of an address phase
followed by one or more data phases. The
21041 supports both read and write bursts.
Little and big endian byte ordering can be
used.
Attachment unit interface and BNC select
line. When asserted high, the 10BASE5 (AUI)
mode is selected. When asserted low, the
10BASE2 (BNC) mode is selected. This output
pin is used mainly to enable the external BNC
transceiver in 10BASE2 mode. This pin is an
input pin in mode 0.
Attachment unit interface receive collision
differential negative data.
Attachment unit interface receive collision
differential positive data.
Attachment unit interface receive differential
negative data.
Attachment unit interface receive differential
positive data.
Attachment unit interface transmit
differential negative data.
Attachment unit interface transmit
differential positive data.
(continued on next page)
aui_bnc
I/O
92
aui_cd–
I
107
aui_cd+
I
106
aui_rd–
I
110
aui_rd+
I
109
aui_td–
O
101
aui_td+
O
100
11
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