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參數(shù)資料
| 型號(hào)： | 21041 |
| 廠商： | Intel Corp. |
| 英文描述： | Digital Semiconductor 21041 PCI Ethernet LAN Controller(數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)LAN控制器) |
| 中文描述： | 數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)局域網(wǎng)控制器（數(shù)字半導(dǎo)體21041的PCI以太網(wǎng)局域網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 21/64頁(yè) |
| 文件大?。?/td> | 230K |
| 代理商： | 21041 |
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Table 4 (Cont.) Quick Pin Reference
Signal
Type
Pin
Number
Description
br_ad<7>
/
sr_din
I/O
93
Boot ROM address and data multiplexed line
bit 7. In two consecutive address cycles, this
pin carries boot ROM address bits 7 and 15.
During the data phase, it contains data.
When the 21041 operates with the serial
ROM, serial ROM data in (
sr_din
) serially
shifts the Ethernet identification address from
the 21041 into the serial ROM device.
During operation with the external register,
this pin is used to carry data bit 7 to and from
the external register.
When mode 0 (21040) is selected, this pin
must be tied to
vss
.
Bits 0 through 3 of the bus command and byte
enable lines. Bus command and byte enable
are multiplexed on the same PCI pins.
During the address phase of the transaction,
c_be_l<3:0>
provide the bus command.
During the data phase,
c_be_l<3:0>
provide
the byte enable. The byte enable determines
which byte lines carry valid data. For
example,
c_be_l<0>
applies to byte 0, and
c_be_l<3>
applies to byte 3.
In all master and I/O operations,
c_be_l<3:0>
contain a value equal to a longword
hexadecimal value of 0. In configuration
operations,
c_be_l<3:0>
can contain any
value; 21041 supports byte, word, and
longword operations.
The clock provides the timing for the 21041–
related bus transactions. All the other bus
signals are sampled on the rising edge of
clk
.
The clock range is between 16 megahertz and
33 megahertz.
(continued on next page)
c_be_l<3:0>
I/O
See
Figure 2.
clk
I
9
13
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