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參數(shù)資料
| 型號： | 20668 |
| 英文描述： | ?lanSC300 Data Sheet ?lanSC310 Data Sheet |
| 中文描述： | ？lanSC300數(shù)據(jù)表？lanSC310數(shù)據(jù)表 |
| 文件頁數(shù)： | 39/119頁 |
| 文件大?。?/td> | 1167K |
| 代理商： | 20668 |
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élanSC310 Microcontroller Data Sheet
39
P R E L I M I N A R Y
one page is spread across both DRAM banks. Both
DRAM modes use standard Fast Page mode DRAMs.
The memory controller operation is synchronous with
respect to the CPU. This ensures maximum perfor-
mance for all transfers to local memory. The clock
stretching implemented by the clock generation cir-
cuitry works to reduce synchronous logic power con-
sumption.
As shown in Table 12, the two DRAM operating modes
are defined by the MOD field in the Memory Configura-
tion Register, Index 66h, bit 0.
T
he élanSC310 microcontroller defaults to a DRAM in-
terface. The SRAM mode is selected via bit 0 of the
Miscellaneous 6 Register Index 70h. The memory con-
troller provides for a direct connection of two 16-bit
banks supporting up to 16 Mbyte of DRAM, utilizing in-
dustry standard modules. The élanSC310 microcon-
troller shares the DRAM address lines MA0–MA11 with
the upper system address lines SA12–SA23 to reduce
pin count. This signal sharing is shown in Table 13.
The élanSC310 microcontroller also shares the DRAM
data bus with the system data bus on the D15–D0 pins.
In a typical system, an SD bus is created with an exter-
nal x 16 bit buffer or level translator to isolate the
DRAM data bus from the rest of the system. Refer to
the Typical System Block Diagram, Figure 7 on page
55 of this data sheet. The DRAM configurations are
supported as shown in Table 14. The bank size infor-
mation in the table also applies when system memory
is configured as SRAM; however, SRAM uses a differ-
ent addressing scheme than DRAM and shares the
same address lines as the ISA bus. Chapter 2 in the
élan
TM
SC310 Microcontroller Programmer’s Refer-
ence Manual
, order #20665, contains more informa-
tion. Note that the configurations that use 512 Kbyte x
8 bit and 1 Mbyte x 16 bit DRAMs employ asymmetrical
addressing. Table 15 and Table 16 show the relation-
ship of the CPU address mapped to the DRAM mem-
ory.
Notes:
1. SRAM configuration is supported. Bit 7 of Index Register B4h must be cleared. Setting MS2–MS0 of Index 66h as specified in
the table selects the SRAM bank sizes.
See Table 15 and Table 16 for the DRAM address multiplexing schemes for normal page mode and Enhanced Page mode, re-
spectively.
Table 12.
DRAM Mode Selection
MOD0 (Index 66h, bit 0)
0
1
Function
Page mode
Enhanced Page mode
Table 13.
MA and SA Signal Pin Sharing
System Address
SA23–SA14
SA13
SA12
DRAM Memory Address
MA9–MA0
MA10
MA11
Table 14.
Supported DRAM/SRAM Configuration
Bank Sizes
(16-Bit Wide Only)
Index B1h
Index
B4h
Index Reg. 66h
Total DRAM/SRAM
Size
512 Kbyte
512 Kbyte
1 Mbyte
1 Mbyte
1 Mbyte
1
Bank 0 DRAMs
Bank 1 DRAMs
Bit 7
Bit 6
Bit 7
MS2
Bit 4
x
x
x
x
0
0
MS1
Bit 3
x
x
x
x
0
1
MS0
Bit 2
x
x
x
x
1
0
4 256K x 4 bits
1 256K x 16 bits
4 256 K x 4 bits
1 256K x 16 bits
2 512 K x 8 bits
2 512 K x 8 bits
—
—
0
0
0
0
x
x
0
0
1
1
x
x
1
1
1
1
0
0
4 256 K x 4 bits
1 256K x 4 bits
—
2 512 K x 8 bits
2 Mbyte
1
2 Mbyte
1
2 Mbyte
4 1 Mbyte x 4 bits
—
x
x
0
0
1
1
1 1 Mbyte x 16 bits
4 1 Mbyte x 4 bits,
—
1
x
0
x
1
0
x
1
x
0
x
0
4 Mbyte
1
4 Mbyte
4 1 M
byte
x 4 bits
1 1 Mbyte x 16 bits
1 1 M
byte
x 16 bits
1
1
1
x
x
x
8 Mbyte
1
4 4 M
byte
x 4 bits
—
x
x
0
1
0
1
16 Mbyte
1
4 4 M
byte
x 4 bits
4 4 M
byte
x 4 bits
x
x
0
1
1
0
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