參數(shù)資料
型號： 20668
英文描述： ?lanSC300 Data Sheet ?lanSC310 Data Sheet
中文描述： ？lanSC300數(shù)據(jù)表？lanSC310數(shù)據(jù)表
文件頁數(shù)： 31/119頁
文件大?。?/td> 1167K
代理商： 20668
élanSC310 Microcontroller Data Sheet
31
P R E L I M I N A R Y
SYSTEM INTERFACE
AEN [TDI]
DMA Address Enable (Output; Active High)
AEN is used to indicate that the current address active
on the SA23–SA0 address bus is a memory address
and that the current cycle is a DMA cycle. All I/O de-
vices should use this signal in decoding their I/O ad-
dresses and should not respond when this signal is
asserted. When AEN is asserted, the DACKx signals
are used to select the appropriate I/O device for the
DMA transfer.
This is a dual-function pin. When the JTAGEN signal is
asserted, it functions as the TDI, JTAG Test Data Input
pin.
D15–D0
System Data Bus (Bidirectional; Active High)
The System Data Bus inputs data during memory and
I/O read cycles, and outputs data during memory and
I/O write cycles. During Local Bus and DRAM/SRAM
cycles, this bus represents the CPU data bus.
DACK2 [TCK]
DMA Channel 2 Acknowledge (Output; Active Low)
This output indicates that the current transfer is a DMA
transfer to the I/O device connected to this DMA chan-
nel. In PC-compatible system designs, this signal can
be connected to the floppy disk controller DMA ac-
knowledge input.
This is a dual-function pin. When the JTAGEN signal is
asserted, it functions as the TCK (JTAG Test Clock)
pin. See
“JTAG Boundary Scan Interface” on page 37
for more information on the function of this pin during
Test mode.
DBUFOE
Data Buffer Output Enable (Output; Active Low)
This output is used to control the output enable on the
system data bus buffer. When Low, the outputs of the
Data Bus Buffer are enabled.
DRQ2 [TDO]
DMA Channel 2 Request (Input; Active High
with Internal Pulldown)
This input is used to request a DMA transfer. It can be
connected to the floppy disk controller DMA request
output in PC-compatible system designs.
This is a dual-function pin. When the JTAGEN signal is
asserted, it will function as the TDO, JTAG Test Data
Out pin. See the “JTAG Boundary Scan Interface” on
page 37 for more information on the function of this pin
during Test mode.
ENDIRH
High Byte Data Buffer Direction Control
(Output; Active High)
This output controls the transceiver on the high byte of
the data bus, bits 15–8. When asserted, this signal is
used to enable the data from the élanSC310 microcon-
troller data bus to the buffered data bus.
ENDIRL
Low Byte Data Buffer Direction Control
(Output; Active High)
This output controls the transceiver on the low byte of
the data bus, bits 7–0. When asserted, this signal is
used to enable the data from the élanSC310 microcon-
troller data bus to the buffered data bus.
IOCHRDY
I/O Channel Ready (Input; Active High)
This signal is used by ISA slave devices to add wait
states to the current transfer. When this signal is deas-
serted, wait states are added.
IOCS16
(Input; Active Low)
This input is used to signal to the ISA control logic that
the targeted I/O device is a 16-bit device.
IOCS16
is generated by a 16-bit ISA I/O expansion
board when the board recognizes it is being ad-
dressed.
IOCS16
provides the same function for 16-bit
I/O expansion devices as the
MCS16
signal provides for
16-bit memory devices.
Note:
IOCS16
is internally ORed with
MCS16
. Do not
tie
IOCS16
Low.
For more information about the
IOCS16
pin, see the
Using 16-Bit
ROMCS
Designs in élan
TM
SC300 and
élanSC310 Microcontrollers Application Note
, order
#21825.
IOR
I/O Read Command (Output; Active Low)
The IOR signal indicates that the current cycle is a read
of the currently selected I/O device. When this signal is
asserted, the selected I/O device can drive data onto
the data bus.
IOW
I/O Write Command (Output; Active Low)
The IOW signal indicates that the current cycle is a
write of the currently selected I/O device. When this
signal is asserted, the selected I/O device can latch
data from the data bus.
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