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參數(shù)資料
| 型號(hào)： | 05F8025 |
| 英文描述： | IC-SM-QUAD 12 BIT DAC |
| 中文描述： | 集成電路釤四路12位DAC |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 502K |
| 代理商： | 05F8025 |
DAC8412/DAC8413
REV. C
–6–
Table I. DAC8412/DAC8413 Logic Table
A1
A0
R/W
CS
RS
LDAC
INPUT REG
OUTPUT REG
MODE
DAC
L
H
L
WRITE
A
L
H
L
H
L
WRITE
B
H
L
H
L
WRITE
C
H
L
H
L
WRITE
D
L
H
WRITE
HOLD
WRITE INPUT
A
L
H
L
H
WRITE
HOLD
WRITE INPUT
B
H
L
H
WRITE
HOLD
WRITE INPUT
C
H
L
H
WRITE
HOLD
WRITE INPUT
D
L
H
L
H
READ
HOLD
READ INPUT
A
L
H
L
H
READ
HOLD
READ INPUT
B
H
L
H
L
H
READ
HOLD
READ INPUT
C
H
L
H
READ
HOLD
READ INPUT
D
X
H
L
HOLD
Update all output registers
All
X
H
HOLD
All
X
L
X
*All registers reset to mid/zero-scale
All
XX
XH
g
X
*All registers latched to mid/zero-scale
All
*DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don’t Care.
DB7
DB8
DB9
DB10
DB11
A1
A0
VREFL
VOUTC
VOUTD
VDD
VLOGIC
CS
R/W
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
V REFH
VOUTB
VOUTA
VSS
RESET
LDAC
R3
ONCE PER PORT
*
V DD
V REFH
V REFL
GND
VSS
D1
C1
C1 C1
D1
C2
N/C
R6
R1
C1
D1
+
++
+
R5
R4
C2
N/C
R1
R2
V
= +15V, V
= –15V, V
= +10V, V
= –10V
R1 = 10
, R2 = 100, R3 = 5k, R4 = 10k, R5 = 100k,
R6 = 47
for LCC, R6 = 100 for DIP
C1 = 4.7
F (ONCE PER PORT), C2 = 0.01F (EACH DEVICE)
D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT)
DD
SS
REFH
REFL
DAC8412/DAC8413 Burn-In Diagram
OPERATION
Introduction
The DAC8412 and DAC8413 are quad, voltage output, 12-bit
DACs featuring a 12-bit data bus with readback capability. The
only differences between the DAC8412 and DAC8413 are the
reset functions. The DAC8412 resets to midscale (code 800H)
and the DAC8413 resets to minimum scale (code 000H).
The ability to operate from a single +5 volt only supply is a
unique feature of these DACs.
dividing the system into three separate functional groups: the
digital I/O and logic, the digital to analog converters and the
output amplifiers.
DACs
Each DAC is a voltage switched, high impedance (R = 50 k
),
R-2R ladder configuration. Each 2R resistor is driven by a pair
of switches that connect the resistor to either VREFH or VREFL.
Reference Inputs
All four DACs share common reference high (VREFH) and refer-
ence low (VREFL) inputs. The voltages applied to these reference
inputs set the output high and low voltage limits of all four of
the DACs. Each reference input has voltage restrictions with re-
spect to the other reference and to the power supplies. The
VREFL can be set at any voltage between VSS and VREFH – 2.5 volts,
and VREFH can be set to any value between +VDD – 2.5 volts and
VREFL + 2.5 volts. Note that because of these restrictions the
DAC8412 references cannot be inverted (i.e., VREFL cannot be
greater than VREFH).
It is important to note that the DAC8412’s VREFH input both
sinks and sources current. Also the input current of both VREFH
and VREFL are code dependent. Many references have limited
current sinking capability and must be buffered with an ampli-
fier to drive VREFH. The VREFL has no such special requirements.
It is recommended that the reference inputs be bypassed with
0.2
F capacitors when operating with ±10 volt references.
Digital I/O
See Table I for digital control logic truth table. Digital I/O con-
sists of a 12-bit wide bidirectional data bus, two register select
inputs, A0 and A1, a R/W input, a RESET input, a Chip Select
(CS), and a Load DAC (LDAC) input. Control of the DACs
and bus direction is determined by these inputs as shown in
Table I. Digital data bits are labeled with the MSB defined as
data bit “11” and the LSB as data bit “0.” All digital pins are
TTL/CMOS compatible.
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