參數(shù)資料
型號(hào): 030_BANK
英文描述: Bank Interleaved Memory System for an Am29030 Microprocessor
中文描述: 銀行交錯(cuò)為Am29030微處理器存儲(chǔ)系統(tǒng)
文件頁數(shù): 8/20頁
文件大小: 263K
代理商: 030_BANK
AMD
16
Bank Interleaved Memory System for an Am29030 Microprocessor
PIN
10
/OE_BANK0
PIN
11
/OE_BANK1
PIN
12
GND
PIN
13
NC
PIN
14
DIV_CLK
PIN
15
/BANK1_CAS3
PIN
16
/BANK1_CAS2
PIN
17
/BANK1_CAS1
PIN
18
/BANK1_CAS0
PIN
19
/BANK0_CAS3
PIN
20
/BANK0_CAS2
PIN
21
/BANK0_CAS1
PIN
22
/BANK0_CAS0
PIN
23
/SECOND_ACCESS
PIN
24
VCC
;––––––––––––––––––––––––––––––––––– Boolean Equation Segment ––––––
EQUATIONS
MINIMIZE_OFF
DIV_CLK := /DIV_CLK
SECOND_ACCESS :=
MEM_RDY
+ SECOND_ACCESS*MEM_ACCESS
BANK0_CAS0 =
REF_ACCESS
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK0*/MEM_RDY*/MEMCLK
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK0*BANK0_CAS0
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK1*MEM_RDY*/MEMCLK
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK0*/WRITE
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK1*/WRITE*/MEMCLK
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*/WRITE*BANK0_CAS0*MEMCLK
+ MEM_ACCESS*MEM_RDY*OE_BANK0*WRITE*WE0*/MEMCLK
BANK0_CAS1 =
REF_ACCESS
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK0*/MEM_RDY*/MEMCLK
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK0*BANK0_CAS1
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK1*MEM_RDY*/MEMCLK
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK0*/WRITE
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK1*/WRITE*/MEMCLK
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*/WRITE*BANK0_CAS1*MEMCLK
+ MEM_ACCESS*MEM_RDY*OE_BANK0*WRITE*WE1*/MEMCLK
BANK0_CAS2 =
REF_ACCESS
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK0*/MEM_RDY*/MEMCLK
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK0*BANK0_CAS2
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK1*MEM_RDY*/MEMCLK
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK0*/WRITE
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK1*/WRITE*/MEMCLK
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*/WRITE*BANK0_CAS2*MEMCLK
+ MEM_ACCESS*MEM_RDY*OE_BANK0*WRITE*WE2*/MEMCLK
BANK0_CAS3 =
REF_ACCESS
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK0*/MEM_RDY*/MEMCLK
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK0*BANK0_CAS3
+ MEM_ACCESS*/SECOND_ACCESS*/WRITE*OE_BANK1*MEM_RDY*/MEMCLK
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK0*/WRITE
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK1*/WRITE*/MEMCLK
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