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參數(shù)資料
| 型號： | 030_BANK |
| 英文描述： | Bank Interleaved Memory System for an Am29030 Microprocessor |
| 中文描述： | 銀行交錯為Am29030微處理器存儲系統(tǒng) |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 263K |
| 代理商： | 030_BANK |
AMD
4
Bank Interleaved Memory System for an Am29030 Microprocessor
counts off 128 DIV_CLK before setting REF_REQ.
REF_REQ is held active until MSTR_CON acknowl-
edges this request by issuing a REF_ACCESS. This
then resets the REF_REQ bit. The count of 256 33-ns
cycles gives a refresh of 8.45
ms, which is an over re-
fresh but accounts for the possibility of an Am29030 pro-
cessor burst losing a whole cycle count in the REFRESH
PAL device.
ADDR_CTR PAL Device
The last PAL device to examine is the ADDR_CTR PAL
device. This device is a 7-bit counter that is in between
the A9–A3 address bits of the Am29030 processor and
the 74F157 address multiplexers. This PAL device has
two control terms: LOAD and INC. All the bits are regis-
tered with the MEM_CLK, making this PAL device a
clocked, loadable, and controllable counter. LOAD is
controlled by IDLE of the MSTR_CON PAL device and
when the master state machine is in IDLE, the output
registers are constantly being updated by their corre-
sponding address bits. When a MEM_ACCESS starts,
the address is held until MSTR_CON gives an INC con-
trol and then the outputs count up by 1.
Additional Considerations
One hidden caveat in both the original and modified de-
signs is that the write signal passes through the 74F157
multiplexers. This is because refresh has priority over
memory accesses, and because 4-Mbyte DRAMs and
above have a new test mode such that if write is Low dur-
ing a CAS before RAS refresh, DRAM is put in a special
test mode. By not making MUX True during a REF_AC-
CESS and by putting WRITE from the processor into the
multiplexer, the problem is not only prevented but the
write signal to the DRAM is buffered.
TIMING ANALYSIS
The timing analysis is simple in this design. There are
four critical paths to examine: the ROM access, the RAS
access, the CAS access, and the OE access.
ROM Access Time
The ROM access is controlled by the processor address
valid time, plus the address access time of the ROM,
plus the Am29030 processor setup time. The equation
is as follows:
T clk–q 29030 + T ROM access + T setup 29030
3 MEMCLKs
This results in a value of 13 + ROM access + 9
99,
making a ROM of access time 77 ns or less acceptable.
AMD makes 70-ns EPROMs so that speed is used for
this design.
RAS Access Time
RAS access time is given by the following equation:
T clk–q 22V10–7 + T RAS access + T setup 29030
3 MEMCLKs
This results in a value of 5 + 80 + 9
99, which is ac-
ceptable.
CAS Access Time
CAS access time is given by the following equation:
T clk–q 22V10–7 + T CAS access + T setup 29030
2 MEMCLKs
This results in a value of 5 + 35 + 9
66, which is ac-
ceptable.
OE Access Time
The real critical-path item is the OE access time. Its
equation is given by the following:
T clk–q 22V10–7 + T OE access + T setup 29030
MEMCLK
This results in a value of 5 + 20 + 9
33, or 34 33.
Although the result is off by 1 ns, it can still be used if all
of the memory subsystem is kept very close to the pro-
cessor to minimize transmission line issues, knowing
that the worst-case timing is always at high temperature,
low voltage, and worst-case parts, simultaneously. This
could be guaranteed in a manufacturing environment by
running the design at 33 MHz for all system tests and
then shipping at 30 MHz as designed.
CONCLUSION
Although bank interleaving is not without an attendant
cost factor and complexity of design, the design pres-
ented in this application note shows how easily an ex-
tension to the original EZ-030 board design can be
made to bring the speed up to double the original design.
The increased complexity turns out to be only one extra
PAL device. A delay line from the original design was
even eliminated. The performance of this modified de-
sign is a 4 clock-cycle first access and single-cycle
burst, while the original EZ-030 board design is a 3
clock-cycle first access and single-cycle burst. The ex-
tra cost of the design is only the increase in the cost of
7.5-ns PAL devices and the extra memory array, plus the
cost of a 33-MHz Am29030 processor as opposed to a
16-MHz Am29030 processor. The performance, while
not quite double, comes close in a very compact design.
SUGGESTED REFERENCE
EZ-030 Demonstration Board Theory of Operation
application note, order# 17580, Advanced Micro De-
vices
Redesigning the EZ-030 Demonstration Board with
a PCI I/O Bus application note, order# 18468, Ad-
vanced Micro Devices
Appendix A. Schematics
The schematics for this design are shown on the pages
that follow.
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