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參數(shù)資料
| 型號： | 030_BANK |
| 英文描述： | Bank Interleaved Memory System for an Am29030 Microprocessor |
| 中文描述： | 銀行交錯為Am29030微處理器存儲系統(tǒng) |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 263K |
| 代理商： | 030_BANK |
AMD
3
Bank Interleaved Memory System for an Am29030 Microprocessor
comes True at the 3-clock cycle from RAS. INC then
starts a division by 2 until all accesses have been com-
pleted. If A2=1 on the first access, INC becomes True
one clock cycle before MEM_RDY becomes True, so as
to increment the CAS address to the next higher bank
before the even bank CAS can be asserted.
MEM_RDY is also a registered term and provides all
ready generation for both DRAM and ROM access. In
MEM_ACCESS, MEM_RDY becomes True once, if
BURST from the Am29030 processor is False on the
first access; or, if BURST is True on the first access,
MEM_RDY stays True as long as BURST stays True
from the Am29030 processor.
ROM access does not use the master state machine but
instead uses the MEM_RDY line to provide one of the
clock cycles of access timing. There are, however, three
cycles that are needed.
The first cycle is a REQ signal from the Am29030 pro-
cessor, with A31=0 and A30=0. Because a ROM access
is taking place, the state bit INC, which controls the ad-
dress pre-counter, is not needed for a REF_ACCESS.
So, in the second cycle, INC is set to True. Finally, in the
third cycle, MEM_RDY is set to True. Then both bits are
set to False as the Am29030 processor changes the ad-
dress on the bus for the next access.
Just as in the EZ-030 board design, this modified design
carries forth the single ROM for boot-up and monitor
code, so the RDN pin is controlled for all ROM accesses
by the ROM_CS term in the MSTR_CON PAL device.
During reset, this pin is False (high) so this signals the
internal logic of the Am29030 processor that a RDN is
8-bits wide as opposed to 16-bits wide.
CAS_DEC PAL Device
The CAS_DEC PAL device has all the CAS signal gen-
eration as well as two extra terms: DIV_CLK and SE-
COND_ACCESS. DIV_CLK clocks the refresh counter
and the I/O control PAL device, which is needed be-
cause of the higher clock rate of this design as
compared to the EZ-030 board design. This keeps the
two PAL devices compatible to their original timing.
SECOND_ACCESS is used in the CAS pulse genera-
tion and controls the INC term in the MSTR_CON PAL
device. It goes True after the first access to DRAM has
taken place and stays True until MEM_ACCESS goes
False.
The CAS pulse generation is the most complicated of
the modifications. There are eight CAS lines: one set of
four for the even bank and one set of four for the odd
bank. Each set of four controls byte-enable access, es-
pecially for writes to memory. Reads are always per-
formed 32 bits (one word) at a time. The equations are
then essentially copies of each other, with only the corre-
sponding byte enable (WEx) used for writes and
OE_BANKx used for bank control (see Equation 1).
The equations are divided into three parts. Part 1 is one
line [1.a] and supports CAS before RAS refresh. Part 3 is
one line [1.h] that controls writes. Writes are simply an
AND of the MEM_CLK and the controlling OE_BANK
term and the WEx term that controls that byte. Part 2 is
the middle six terms [1.b–1.g] and forms the read pulse
shaping. The CAS pulse starts out with SECOND_AC-
CESS False and the OE_BANK control True [1.b]. CAS
is then held True as a regenerative latch [1.c] if it does go
True. It is also held True through an entire cycle if SE-
COND_ACCESS is False and MEM_RDY is True [1.d].
When the SECOND_ACCESS term is True, the next
three lines [1.e–1.g] form a pulse that makes CAS for
this bank False for half a clock cycle on the opposite
bank access [1.e]. This CAS False gets the new address
in the CAS address latch on the inside of the DRAMs.
Then the next line [1.f] provides a cross term to prevent
output glitches while the OE_BANK term switches, and
then the CAS is held True for the entire cycle that its own
OE_BANK is True. All these equations [1.e–1.g] then
provide a CAS pulse that is False for half a clock cycle,
and True for the rest of the clock cycle and then the next
full clock cycle, making the 2 clock-cycle access. Be-
cause of the higher clock frequency that provides a half
clock cycle of 16.5 ns, no delay line is needed in this de-
sign as was needed in the EZ-030 board design. Note
also in the PAL equation section that minimization is
turned off for all the CAS equations because the cross
term is logically redundant (but not from a timing stand-
point) and if minimized out would create glitches on the
CAS line that would adversely effect the DRAMs.
REFRESH PAL Device
The REFRESH PAL device is identical to the one used in
the EZ-030 board design and is a 7-bit counter that
Equation 1. CAS_DEC PAL Equation
BANK0_CAS0 = REF_ACCESS
[1.a]
+ MEM_ACCESS*SECOND_ACCESS*WRITE*OE_BANK0*MEM_RDY*MEMCLK
[1.b]
+ MEM_ACCESS*SECOND_ACCESS*WRITE*OE_BANK0*BANK0_CAS0
[1.c]
+ MEM_ACCESS*SECOND_ACCESS*WRITE*OE_BANK1*MEM_RDY*MEMCLK
[1.d]
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK0*WRITE
[1.e]
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*OE_BANK1*WRITE*MEMCLK
[1.f]
+ MEM_ACCESS*SECOND_ACCESS*MEM_RDY*WRITE*BANK0_CAS0*MEMCLK
[1.g]
+ MEM_ACCESS*MEM_RDY*OE_BANK0*WRITE*WE0*MEMCLK
[1.h]
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