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| 型號(hào)： | 030_BANK |
| 英文描述： | Bank Interleaved Memory System for an Am29030 Microprocessor |
| 中文描述： | 銀行交錯(cuò)為Am29030微處理器存儲(chǔ)系統(tǒng) |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 263K |
| 代理商： | 030_BANK |
AMD
2
Bank Interleaved Memory System for an Am29030 Microprocessor
16V8 MSTR_CON PAL device in the EZ-030 board de-
sign to a 22V10. In addition, the RDY term in the EZ-030
board MSTL_CTL PAL device is moved outside all the
PAL devices and put in a simple 74F08 used to OR the
two sources of RDY (MEM_RDY and SERIAL_RDY) for
the processor.
Change the CAS_DEC PAL Device
The third design change centers around the memory
subsystem. The two banks are common in their RAS
generation and address multiplexing, but the CAS gen-
eration must take into account the two separate banks
as well as the need to be byte-writable on an individual
basis. This requires 10 outputs for this function, so the
CAS_DEC PAL device in the EZ-030 board design is
now replaced with another 22V10.
These are the needed design changes at a high level;
the next section looks at the PAL devices in more detail.
THEORY OF OPERATION
The
MSTR_CON,
CAS_DEC,
REFRESH,
and
ADD_CTR PAL devices are discussed in the following
sections. The PAL equations referenced are provided in
Appendix B at the end of the document. (The SERIAL
PAL device is the same as that discussed in the EZ-030
board application note; the SERIAL PAL equations are
shown in Appendix B.) Appendix A contains the sche-
matics for the design.
MSTR_CON PAL Device
The state machine in the MSTR_CON PAL device rep-
resents the heart of the bank interleaved memory de-
sign. It controls the main memory functions of both the
DRAM access and the refresh of the DRAMs, and also
provides decoding and timing for the ROM access. This
is done in a way that hides the refreshes so they do not
impact performance; for example, DRAM refresh can be
performed while ROM is being accessed. Additionally,
state bits are shared between state machines so that ex-
tra flip-flops are not needed. For example, this sharing is
done for ROM access because a 3-cycle access on
ROM is needed at 30 MHz, while in 16 MHz only 2 cycles
are needed. So a simple division by 2 needs to change
to a division by 3, which requires one more state bit.
The state machine in Figure 1 shows the normal path of
the EZ-030 board design, where IDLE is the state in
which the machine is at rest and is ready to arbitrate a
decision as to which path is chosen.
A refresh has priority in the arbiter, so a REF_ACCESS
is taken regardless of the state of REQ in the Am29030
processor. MEM_ACCESS is taken only when there is
no REF_REQ with a REQ, and when the address lines
A31=1 and A30=0 are valid. The last state of CAS in the
MEM_ACCESS holds and MEM_RDY is driven True in
this state until the BURST signal from the Am29030 pro-
cessor goes False.
REF_ACCESS
BURST
Figure 1. State Diagram
IDLE
CAS
RAS
RAS1
CAS1
RAS2
CAS2
All
REF_ACCESS
MEM_ACCESS*
BURST
VCC
states
False
RESET
18478A-1
MEM_ACCESS*REF_ACCESS
If the BURST signal is False when REQ is asserted at
the beginning of an access, this is a single access and
the machine goes to the bottom and cycles back around.
An extra precharge clock cycle is needed at the end of a
memory cycle to ensure that no two accesses are too
close. This is accomplished by waiting until all state bits
go False before moving to the IDLE state. Once the state
machine moves to IDLE, it can re-arbitrate. Because the
IDLE cycle occurs before either RAS or CAS can be as-
serted, this ensures that 2 clock cycles are performed on
back-to-back accesses with RAS False, which meets
the precharge requirement.
OE_BANK0 serves as a dual-function signal to the state
machine. It is used on MEM_ACCESS to enable the
even bank and is normally a division by 2 in a burst se-
quence. However, a new state is needed in REF_AC-
CESS to time the memory cycle so, in a refresh cycle,
OE_BANK0 is used to signal the last state (RAS2) of a
refresh cycle. OE_BANK0 and OE_BANK_1 are also
used in MEM_ACCESS to provide an indication of the
last state as well as provide the output enable (OE) mul-
tiplexing for the DRAMs.
The remaining signals used for a DRAM access are
RAS, INC, and MEM_RDY. RAS is a term that is regis-
tered to provide the highest speed to the memory inter-
face. RAS has the same timing as MEM_ACCESS, or is
delayed by one clock so that a REF_ACCESS can pro-
vide the CAS-before-RAS signaling for a refresh.
INC controls the incrementing of the address counter on
the Am29030 processor’s A9–A3 bits. INC is a regis-
tered term for ease of state control. It becomes True in
an access that starts with A2=0, as MEM_RDY be-
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