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| 型號： | 030_BANK |
| 英文描述： | Bank Interleaved Memory System for an Am29030 Microprocessor |
| 中文描述： | 銀行交錯為Am29030微處理器存儲系統(tǒng) |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 263K |
| 代理商： | 030_BANK |
Publication# 18478
Rev. A
Amendment /0
Issue Date: May 1994
Bank Interleaved Memory System
for an Am29030
t Microprocessor
Application Note
by David Stoenner
Advanced
Micro
Devices
This application note explains how to modify the EZ-030 demonstration board to increase the bus
speed from 16 MHz to 30 MHz.
INTRODUCTION
Although memory has grown faster over the years,
memory speed has not kept up with the speed of proces-
sors or the demand for even faster microprocessor sys-
tems, be they desktop or embedded. The EZ-030
demonstration board addresses the need for a low-cost
and simple memory system for the AMD Family of
Am29030 microprocessor RISC-based machines, yet it
is limited to a maximum bus speed of 16 MHz (see the
EZ-030 Demonstration Board Theory of Operation ap-
plication note for more information). When faster memo-
ries, faster PAL
r devices, and faster multiplexers
(74F157s) are substituted in the EZ-030 board design,
20 MHz is possible, but only in PGA versions.
Somewhere in the gray area of 20 to 25 MHz is the point
where memory can no longer be single-cycled out of
one memory bank. The limiting factor is the CAS access
time and the processor setup time for data. However,
DRAMs have a shorter data valid time from their output
enable. So, if two banks are connected at the data pins
and then independently cycled and the output enable
(OE) of each bank is used to multiplex the values togeth-
er, the memories can support the single-cycle access for
which the 29K
t Family is so famous. This technique is
called
bank interleaving.
This application note explains how a few simple en-
hancements to the EZ-030 logic design, along with
another memory bank, can extend the upper frequency
limit to 30 MHz.
CHANGES TO DESIGN
To achieve a 30-MHz speed, make the following
changes to the EZ-030 logic design:
Replace the 16-MHz Am29030 processor with a
33-MHz Am29030 processor
Add a memory bank
Add an extra 16V8 to the lower address lines of the
Am29030 processor for advanced counting
Change the MSTR_CON PAL device from a 16V8 to
a 22V10
Change the CAS_DEC PAL device from a 16V8 to a
22V10
Add a Memory Bank and a Counter
In a bank interleaved memory design, two memory sys-
tems with their outputs connected together form a single
data bus. While one bank provides data for the current
cycle, the other bank gets the next value. This requires
the new bank to be ahead of the current bank, which re-
quires an address one greater than what the processor
provides. This is accomplished in the design by adding a
counter on the lower processor address lines that drives
the CAS addresses in the memory bank. Processor ad-
dress A2 is used to select between banks while A9–A3
drive CAS A6–A0. This means the count can be loaded,
incremented, or held in the counter. Since the CAS ad-
dress is not needed until the second clock cycle, there is
plenty of time to get the counter up-to-date with the cor-
rect address.
Note that this counter needs to be pre-incremented if the
burst starts at an address boundary where A2 of the ac-
cess is 1. In this case, the odd memory bank starts up
first but the counter is quickly incremented to the next
value, so the new CAS can start the even bank access at
the next larger A9–A3 value. No address counting past
A9 is needed since internal address comparators on the
Am29030 processor stop all burst transactions on the
bus at 1K boundaries.
Change the MSTR_CON PAL Device
The second design change is in the master state ma-
chine. Since the clock is now higher in frequency but the
memories are not any faster, the first access must have
a greater number of clock cycles to have the same time
value as those at 16 MHz. The memories used are 80-ns
RAS access DRAMs, so at least a 3 clock-cycle access
is needed once a RAS is started. RAS is not started until
a REQ from the processor has been asserted for one
clock cycle, which makes the first access in this memory
system 4 clocks.
The other value that must be accounted for is RAS pre-
charge, the value that RAS is de-asserted before the
next RAS access. This value is 50 ns in 80-ns memory,
which was 1 clock at 16 MHz but is now 2 clocks at
30 MHz. Both of these requirements add two more
states to the master control PAL device and thereby ne-
cessitate a larger number of outputs than was in the pre-
vious design. This is accomplished by changing the
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