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CHAPTER 7 REGISTERS
345
(24) Performance counter point register 1 (PCPR1)
This register is used to indicate, for each of the window registers, the byte of the load register to be read
next.
Register name
D7
D6
D5
D4
D3
D2
D1
D0
Address
Default
R/W
PCPR1
B1EC B2EC1 B2EC0 B3EC LFBC1 LFBC0 PFBC
FJC
19H
00H
R/W
Field
Function
Default value
Used to indicate which part of B1ECNTR is to be read next.
1
The high-order eight bits of B1ECNTR [15-8] are read next.
D7: B1EC
0
The low-order eight bits of B1ECNTR [7-0] are read next.
0
Used to indicate which part of B2ECNTR is to be read next.
B2EC[1:0]
Part of B2ECNTR to be read next
00
Low-order eight bits [7-0]
01
Middle eight bits [15-8]
10
High-order four bits [19-16]
00
D6: B2EC1
D5: B2EC0
Used to indicate which part of B3ECNTR is to be read next.
1
The high-order eight bits of B3ECNTR [15-8] are read next.
D4: B3EC
0
The low-order eight bits of B3ECNTR [7-0] are read next.
0
Used to indicate which part of LFBCNTR is to be read next.
LFBC[1:0]
Part of LFBCNTR to be read next
00
Low-order eight bits [7-0]
01
Middle eight bits [15-8]
10
High-order four bits [19-16]
D3: LFBC1
D2: LFBC0
00
Used to indicate which part of PFBCNTR is to be read next.
1
The high-order eight bits of PFBCNTR [15-8] are read next.
D1: PFBC
0
The low-order eight bits of PFBCNTR [7-0] are read next.
0
Used to indicate which part of FJCNTR is to be read next.
1
The high-order four bits or FJCNTR [11-8] are read next.
D0: FJC
0
The low-order eight bits of FJCNTR [7-0] are read next.
0