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CHAPTER 7 REGISTERS
299
(3) IMR (interrupt mask register)
Address:
02H
Access mode: Read/write
The IMR register masks or unmasks the issue of an interrupt from each interrupt source. Mask bits
corresponding to the bits of the GSR register are located at the same positions in the IMR register. When
the bit of the GSR register corresponding to an unmasked bit is set to 1, the corresponding interrupt output
pin is made active.
31
0
MASK
Field
Function
Value after reset
Mask
Mask bit corresponding to each bit of GSR register is located at same
position in mask register.
0: Mask
1: Unmask. When 1 is set in GSR register, corresponding interrupt is
issued.
All 0. All interrupts are
masked.
(4) RQU (free buffer underflow register)
Address:
03H
Access mode: Read only
The RQU register bit is set to 1 when the pool corresponding to that bit no longer has a free buffer.
If any one of the bits of this register is set to 1, the RQU bit of the GSR register is set to 1. The
μ
PD98405
detects that no free buffer is available when it has received a cell and transfers its data to the system
memory. Until free buffers again become available, any VC cells that are set in a pool having no free
buffers are discarded, and this bit is set every time a new packet arrives.
31
0
Field
Function
Value after reset
Receive
Queue
Underflow
Bit 0 corresponds to pool 0 and bit 31 corresponds to pool 31. '1'
indicates that pool corresponding to that bit no longer has a free buffer.
All 0