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CHAPTER 6 PHY FUNCTION
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Table 6-14. Set/Reset Conditions for Interrupt Register Bits
Reset conditions
Interrupt mode 2
RCM[1:0] bit = 01
Cause is cleared
Register
name
Bit name
Set conditions
Interrupt mode 1
RCM[1:0] bit = 00
This register is read
(Cause of the interrupt
must have been
cleared)
Interrupt mode 3
RCM[1:0] bit = 1x
This register is read
(Whether cause of the
interrupt is continued
or cleared is
irrelevant)
This register is read
(Whether cause of the
interrupt of the ACR
register is continued
or cleared is
irrelevant)
This register is read
(Whether cause of the
interrupt of the PCR
register is continued
or cleared is
irrelevant)
This register is read
(Whether cause of the
interrupt of the
PCOCR1 and
PCOCR2 registers
continued or cleared
is irrelevant)
This register is read
(Whether cause of the
interrupt is continued
or cleared is
irrelevant)
This register is read
(Whether cause of the
interrupt is continued
or cleared is
irrelevant)
OOL
LOF
LOS
Occurrence of each cause
ALM
Any bit of the ACR register
is set
This register is read
(All bits of the ACR
register must be set to
0)
All bits of the ACR
register are set to 0
PFM
Any bit of the PCR register
is set
This register is read
(All bits of the PCR
register must be set to
0)
All bits of the PCR
register are set to 0
PCO
Any bit of the PCOCR1 and
PCOCR2 registers is set
This register is read
(All bits of the
PCOCR1 and
PCOCR2 registers
must be set to 0)
All bits of the PCOCR1
and PCOCR2 registers
are set to 0
PICR
RFO
Receive FIFO overrun
This register is read
(Cause of the interrupt
must have been
cleared)
Cause of the interrupt
is cleared
ACR
OOF
LOP
OCD
LCD
LAIS
PAIS
LRDI
PRDI
FJ
B1E
B2E
B3E
LFEB
PFEB
B1EC
B2EC
B3EC
LFBC
PFBC
FJC
HECC
FULC
IDLC
INFC
Occurrence of each cause
This register is read
(Cause of the interrupt
must have been
cleared)
Cause of the interrupt
is cleared
PCR
Occurrence of each cause
This register is read
(Whether cause of the
interrupt is continued
or cleared is irrelevant)
This register is read
(Whether cause of the
interrupt is continued or
cleared is irrelevant)
This register is read
(Whether cause of the
interrupt is continued
or cleared is
irrelevant)
PCOCR1
Counter value becomes all
FF
This register is read
(Whether cause of the
interrupt is continued
or cleared is irrelevant)
This register is read
(Whether cause of the
interrupt is continued or
cleared is irrelevant)
This register is read
(Whether cause of the
interrupt is continued
or cleared is
irrelevant)
PCOCR2
Counter value becomes all
FF
This register is read
(Whether cause of the
interrupt is continued
or cleared is irrelevant)
This register is read
(Whether cause of the
interrupt is continued or
cleared is irrelevant)
This register is read
(Whether cause of the
interrupt is continued
or cleared is
irrelevant)