參數(shù)資料
型號(hào)： ZR36506
英文描述： Fast Recovery Rectifier Diodes
中文描述： 外圍芯片
文件頁數(shù)： 86/99頁
文件大小： 452K
代理商： ZR36506
Zoran ZR36506 USBV ision – Datasheet
Zoran Proprietary and Confidential
14 -2
Audio Channel
In addition to the AUDIO_CONT register, there is the AUD_PK_LEN register (Register address
= 51), to select the maximum packet size to be sent via the audio Isochronous pipe. This number
is limited to 128, which is the maximum number of bytes that the ZR36506 audio FIFO can
contain. The software driver should set this register to a value that fits the USB descriptor for the
EP#3 maximum packet length (which is 66, if not using an external EEPROM).
Codec I nterface
The Codec Interface is Long Frame Sync Timing based. The BCLK frequency may be selected
to be – 2048 KHz, 1536 KHz, or 64 KHz, which enables the designer to use almost any family of
low cost Codecs available on the market.
In the Long Frame Sync Timing modes, the MSb of the "transmitted" data is always expected
soon after the rising edge of the FS_L (or FS_R) signal. The ZR36506 produces a positive pulse
of 2 BCLK cycles in these output pins every 125 us (8 KHz) or every 62.5 us (16 KHz), which
indicates the start of sample as specified in the following waveform diagram:
MSb
LSb
Txs
Txd1
Txd2
Tsx
BCLK
FS_L
FS_R
DAT_IN
XX
XX
The BCLK is derived from the 12 MHz clock on the crystal. This results in a 4.3% jitter at the
BCLK signal.
The following table specifies the minimum and maximum time intervals for the Codec Interface
waveform diagram:
Parameter
Symbol
Min
Max Unit
Hold Time from BCLK Low to FS_L / FS_R
High
Txs
180
-
ns
Setup Time from FS_L / FS_R High to BCLK
Low
Tsx
180
-
ns
Delay Time to valid data from FS_L / FS_R
Txd1
-
200
ns
Delay Time from BCLK High to DAT_IN valid
Txd2
-
200
ns
Jitter at the Bit Clock signal BCLK
Cj
-
4.3
%
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