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參數(shù)資料
| 型號： | ZR36067 |
| 廠商： | Zoran Corporation |
| 英文描述： | PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）) |
| 中文描述： | PCI適配器預(yù)定在PCI系統(tǒng)的多媒體應(yīng)用（個PCI（外圍部件互連）適配器（用于的PCI系統(tǒng)的多媒體）） |
| 文件頁數(shù)： | 33/48頁 |
| 文件大?。?/td> | 580K |
| 代理商： | ZR36067 |
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33
AV PCI CONTROLLER
13.20 JPEG Mode and Control
This register contains the JPEG Mode configuration and optional
control bits.
13.21 JPEG Process Control
This register contains the JPEG process control.
Address Offset: 0x100
Bit
Type
Mod
Description
31
RW
all
JPG
- JPEG/MPEG mode selection. This bit
selects between the two code DMA controller
modes.
‘1’ - JPEG Mode.
‘0’ - MPEG Mode.
Default value is ‘0‘
30 : 29
RW
jpg
JPGMode
- JPEG Sub-Modes Selection.
These two bits configure the JPEG sub-
mode.
11b - Motion Video Compression.
10b - Motion Video Decompression.
01b - Still Image Compression.
00b - Still Image Decompression.
Default value is 11b
28 : 7
R
Reserved. Returns zero.
6
RW
jpg
RTBSY_FB
- RTBSY Feed-Back. Enables
the ZR36067 to de-assert the PXEN signal if
RTBSY is detected in the active area of the
field.
‘1’ - Enable PXEN de-assertion if RTBSY is
detected. Allowed only if SyncMstr=1.
‘0’ - Disable PXEN de-assertion.
Default value is ‘0’
5
RW
Go_en
- The enable bit of the ZR36060
START or ZR36050 GO command cycle. The
bit, when ‘1’, enables the GuestBus Master to
perform a JPEG START or GO cycle. During
a JPEG GO cycle the ZR36067 assumes that
the correct address (0x00h) is pre-latched in
an external address register. It is the host’s
responsibility to perform the write operation to
load the address. The host must de-assert
Go_en whenever it accesses the ZR36050
(using PostOffice) in a middle of a JPEG
process, or changes the address latched in
the external register. The host must also de-
assert Go_en before PostOffice pseudo
write-through burst cycles. In this case, the
host also has to wait at least 0.5 microsec-
onds before initiating the burst (to allow the
JPEG START or GO cycle to complete, if one
was started).
Default value is ‘0’ (Not enabled).
4
RW
jpg
SyncMstr
- Sync Signals Master. This bit
configures the ZR36067 as a sync master.
This configuration is allowed in all JPEG
modes except Motion Video Compression
‘1’ - The ZR36067 is the sync signal master.
‘0’ - The sync signals are driven from an
external video source.
Default value is ‘0’
3
RW
jpg
Fld_per_buff
- Number of Fields Per Code
Buffer. This bit reflects the system memory
code buffer structure, in JPEG Compression
and Decompression modes.
‘1’ - The code buffer contains one code field.
‘0’ - The code buffer contains two consecutive
code fields, one code frame.
Default value is ‘0‘
2
RW
jpg
VFIFO_FB
- VFIFO Feed-Back. Enables the
ZR36067 to de-assert the PXEN signal
according to the status of the Video FIFO.
‘1’ - Enable PXEN de-assertion if the pixel
buffer is close to overflow. Allowed only if
SyncMstr=1.
‘0’ - Disable PXEN de-assertion if the pixel
buffer is close to overflow.
Default value is ‘0’
1
RW
jpg
CFIFO_FB
- CFIFO Feed-Back. Enables the
ZR36067 to de-assert the PXEN signal
according to the status of the Code FIFO.
‘1’ - Enable PXEN de-assertion if the code
buffer is close to overflow/underflow. Allowed
only if SyncMstr=1.
‘0’ - Disable PXEN de-assertion if the code
buffer is close to overflow/underflow.
Default value is ‘0’
0
RW
jpg
Still_LitEndian
- Still image pixel Little
Endian format selector. This control bit
defines the pixel format in Still Image Com-
pression and Decompression.
‘1’ - The pixel format is Little Endian.
‘0’ - The pixel format is Gib Endian.
Default value is ‘1’.
Address Offset: 0x104
Bit
Type
Mod
Description
31: 8
R
Reserved. Returns zero.
7
RW
all
P_reset
- Process Reset. This bit is asserted
by the host in order to reset the ZR36067
JPEG-related state machines. The bit must
be asserted at the beginning of a JPEG
process. While it is asserted, all of the JPEG
process parameters may be configured by
the host.
‘1’ - No reset.
‘0’ - Reset.
Default value is ‘1’.
6
R
Reserved, Returns zero.
5
RW
CodTrnsEn
- JPEG Code Transfer Enable.
This bit enables the code transfer between
the internal code buffer and the system
memory in all of the JPEG modes.
‘1’ - Code transfer is enabled.
‘0’ - code transfer is disabled.
Default value is ‘0’.
Address Offset: 0x100 (Continued)
Bit
Type
Mod
Description
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