參數(shù)資料
型號(hào)： ZR36067
廠(chǎng)商： Zoran Corporation
英文描述： PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）)
中文描述： PCI適配器預(yù)定在PCI系統(tǒng)的多媒體應(yīng)用（個(gè)PCI（外圍部件互連）適配器（用于的PCI系統(tǒng)的多媒體））
文件頁(yè)數(shù)： 24/48頁(yè)
文件大?。?/td> 580K
代理商： ZR36067
24
AV PCI CONTROLLER
12.0 PCI CONFIGURATION SPACE REGISTERS
The PCI specification requires that a PCI device include a con-
figuration register space, a set of 256 8-bit configuration
registers. The first 64 bytes make up the configuration header,
predefined by the specification and the remainder are applica-
tion specific. These registers allow device relocation, device
independent system address map construction and automatic
configurations. How the configuration registers are accessed by
the host software is platform dependent; the host PCI bridge is
responsible for translating the host accesses to a PCI configura-
tion cycle, including the assertion of the IDSEL input. The
ZR36067 then responds to these cycles. This section details the
ZR36067’s PCI configuration registers. PCI configuration
accesses to ZR36067 configuration addresses that are not
explicitly described here return zeros (in reads).
Table 14: ZR36067 PCI Configuration Space Registers
Address Offset
Bits
Type
Description
0x00
31:16
R
Device ID. Hardwired to 0x6057.
15:0
R
Vendor ID. Hardwired to 0x11DE.
0x04
31
RC
Parity Error Detected. This bit is set when a parity error is detected, regardless of the Parity Error
Response bit.
30
R
System Error Signaled. Hardwired to ‘0’.
29
RC
Master Abort Detected. This bit is set when a master-abort condition has been detected.
28
RC
Target Abort Detected. This bit is set when a target-abort condition has been detected.
27
RC
Target Abort Signaled. When the ZR36067 terminates a transaction as a target (e.g., due to wrong
address parity) it sets this bit.
26:25
R
DEVSEL Timing. Hardwired to ‘00’ (“fast” timing, i.e., DEVSEL
is asserted before rising edge of clock
three within a cycle).
24
R
Data Parity Reported. Hardwired to ‘0’.
23
R
Fast Back-to-Back Capability. Hardwired to ‘0’.
22:16
R
Reserved. Returns zeros.
15:10
R
Reserved. Returns zeros.
9
R
Fast Back-to-Back Enable. Hardwired to ‘0’.
8
R
System Error Enable. Hardwired to ‘0’.
7
R
Wait Cycle (Stepping) Enable. Hardwired to ‘0’.
6
R
Parity Error Response. Hardwired to ‘0’.
5:3
R
Unused. Hardwired to ‘0’.
2
RW
Master Enable. When this bit is set to ‘1’ the ZR36067 can operate as a bus master. Default is ‘0’.
1
RW
Memory Access Enable. When this bit is set to one the device responds to PCI memory accesses.
Default value is ‘0’.
0
R
I/O Access Enable. Hardwired to ‘0’.
0x08
31:8
R
Class Code. Returns 0x040000 (Multimedia Video Device)
7:0
R
Revision ID. Hardwired to 0x02
0x0C
31:24
R
Unused. Return zeros.
23:16
R
Header Type. Returns zeros.
15:8
RW
Master Latency Timer. The number of PCI clocks that limit ZR36067-initiated bursts in case GNT is
deasserted by the bus arbiter during the ZR36067-initiated burst. The 3 LS bits are read-only zeros.
The default value is 0x00.
7:0
R
Unused. Returns zeros.
0x10
31:12
11:0
RW
R
Memory Base Address. This value determines the base address of the ZR36067 as a memory-
mapped device. The ZR36067 occupies a range of 4096 bytes out of the memory map: Bits 11:0 are
hardwired to ‘0’. The default value of all other bits is ‘0’.
0x14 to 0x2B
R
Hardwired to ‘0’.
0x2C
31:16
R
Subsystem ID. See Section 11.1
15:0
R
Subsystem Vendor ID. See Section 11.2
0x30 to 0x3B
R
Hardwired to ‘0’.
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