參數(shù)資料
型號(hào)： ZPSD301V
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有12個(gè)輸入）
文件頁(yè)數(shù)： 9/90頁(yè)
文件大?。?/td> 491K
代理商： ZPSD301V
ZPSD3XX Famly
3-9
Description
This pin has two configurations. When it is CSI (A19/CSI = 0) and
the pin is asserted high, the device is deselected and powered
down. (See Tables 12 and 13 for the chip state during power-down
mode.) If the pin is asserted low, the chip is in normal operational
mode. When it is configured as A19, (A19/CSI = 1), this pin
can be used as an additional input to the PAD. CADLOG3 = 1
(CATD = 1 for ZPSD3X1) defines the pin as an address;
CADLOG3 = 0 (CATD = 0 for ZPSD3X1) defines it as a logic input.
If it is an address, A19 can be latched with ALE (CADDHLT = 1) or
be a transparent logic input (CADDHLT = 0). In this mode, there is
no power-down capability.
The user-programmable pin can be configured to reset on high
level (CRESET = 1) or on low level (CRESET = 0). It should
remain active for at least 100 ns. See Tables 10a, 10b and 11
for the chip state after reset.
In the multiplexed modes, the ALE pin functions as an Address
Latch Enable or as an Address strobe and can be configured as
an active high or active low signal. The ALE or AS trailing edge
latches lines AD15/A15–AD0/A0 and A16–A19 in 16-bit mode
(AD7/A7–AD0/A0 and A16–A19 in 8-bit mode) and BHE,
depending on the ZPSD3XX configuration. See Table 8. In the
non-multiplexed modes (ZPSD3X2/3X3/3X4R), it can be used as a
general-purpose logic input to the PAD.
PA7–PA0 is an 8-bit port that can be configured to track
AD7/A7–AD0/A0 from the input (CPAF2 = 1). Otherwise
(CPAF2 = 0), each bit can be configured separately as an I/O or
lower-order latched address line. When configured as an I/O
(CPAF1 = 0), the direction of the pin is defined by its direction bit,
which resides in the direction register. If a pin is an I/O output, its
data bit (which resides in the data register) comes out. When it is
configured as a low-order address line (CPAF1 =1), A7–A0
can be made the corresponding output through this port (e.g., PA6
can be configured to be the A6 address line). Each port bit
can be a CMOS output (CPACOD = 0) or an open drain output
(CPACOD = 1). When the chip is in non-multiplexed mode
(CADDRAT = 0), the port becomes the data bus lines (D0–D7).
See Figure 5.
PB7–PB0 is an 8-bit port for which each bit can be configured as
an I/O (CPBF = 1) or chip-select output (CPBF = 0). Each port bit
can be a CMOS output (CPBCOD = 0) or an open drain output
(CPBCOD = 1). When configured as an I/O, the direction of the
pin is defined by its direction bit, which resides in the direction
register. If a pin is an I/O output, its data (which resides in the data
register) comes out. When configured as a chip-select output,
CS0–CS3 are a function of up to four product terms of the inputs to
the PAD B; CS4–CS7 then are each a function of up to two
product terms. On the ZPSD301/302/303/3X4R, when the chip is
in non-multiplexed mode (CADDRAT = 0) and the data bus width
is 16 (CDATA = 1), the port becomes the data bus (D8–D15).
See Figure 7.
Table 1.
ZPSD3XX Pin
Descriptions
(Cont.)
Name
Type
A19/CSI
I
RESET
*
I
ALE
or
AS
I
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
I/O
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
I/O
*
Reset is active low (only) on ZPSD3XXV versions.
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