參數(shù)資料
型號(hào): ZPSD304RV
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗,無SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備(可編程邏輯,零功耗,無的SRAM,19余個(gè)可編程輸入/輸出,通用PLD的有16個(gè)輸入)
文件頁數(shù): 1/90頁
文件大?。?/td> 491K
代理商: ZPSD304RV
3-1
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Single Chip Zero Power Programmable Peripheral for Microcontroller-based
Applications
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Integrated Power Management
— Standby typically 10μA (ZPSD3XX) or 1 μA (ZPSD3XXV)
— Extremely low AC power
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Wide Operating Voltage Range
— V-Versions = 2.7 to 5.5 volts
— Others = 4.5 to 5.5 volts
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19 Individually Configurable I/O pins that can be used as
— Microcontroller I/O port expansion
— Zero Power Programmable Address Decoder (PAD) I/O
— Latched address output
— Open drain or CMOS
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Two Zero Power Programmable Arrays (PAD A and PAD B)
— Total of 40 Product Terms and up to 16 Inputs and 24 Outputs
— Address Decoding up to 1 MB
— Logic replacement
— Turbo Bit to control speed/power
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“No Glue” Microcontroller Chip-Set
— Built-in address latches for multiplexed address/data bus
— Non-multiplexed address/data bus mode
— ALE and Reset polarity programmable
— Selectable modes for read and write control input
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256 Kb, 512 Kb, 1 Mbits, or 2 Mbits of Zero Power UV EPROM
(2 Mbit version is SRAMless)
— Configurable x8 or x16
— Divides into 8 equal mappable blocks for optimized mapping
— 70 ns EPROM access time, including input latches and PAD address decoding.
— Block resolution is from 4K x 8 or 2K x 16 (ZPSD3X1) to
32K x 8 or 16K x 16 (ZPSD3X4R)
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16 Kbit Zero Power Static RAM (SRAM)
— Configurable as 2K x 8 or as 1K x 16
— 70 ns SRAM access time, including input latches and PAD address decoding
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Power Management
— CMiser Bit: Programmable option to reduce AC power consumption
— Turbo Bit: Volatile bit set to achieve zero DC power
Key Features
Programmable Peripheral
ZPSD3XX Famly
Field-Programmable Microcontroller Peripheral
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