- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382772 > ZPSD304RV Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，無SRAM,19個可編程I/O,通用PLD有16個輸入) PDF資料下載
參數(shù)資料
| 型號： | ZPSD304RV |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，無SRAM,19個可編程I/O,通用PLD有16個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，無的SRAM，19余個可編程輸入/輸出，通用PLD的有16個輸入） |
| 文件頁數(shù)： | 20/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | ZPSD304RV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
ZPSD3XX Famly
3-20
Port A in Non-Multiplexed Address/Data Mode
In this mode, Port A becomes the low order data bus byte of the chip. When reading an
internal location, data is presented on Port A pins. When writing to an internal location, data
present on Port A pins is written to that location.
Port B in Multiplexed Address/Data and in 8-Bit Non-Multiplexed Modes
The default configuration of Port B is I/O. In this mode, every pin can be set as an input or
output by writing into the respective pin’s direction flip flop (DIR FF, in Figure 7). As an
output, the pin level can be controlled by writing into the respective pin’s data flip flop
(DFF, in Figure 7). When DIR FF = 1, the pin is configured as an output. When DIR FF = 0,
the pin is configured as an input. The controller can read the DIR FF bits by accessing the
READ DIR register; it can read the DFF bits by accessing the READ DATA register.
Port B pin levels can be read by accessing the READ PIN register. Individual pins can be
configured as CMOS or open drain outputs. Open drain pins require external pull-up
resistors. For addressing information, refer to Tables 6 and 7.
Alternately, each bit of Port B can be configured to provide a chip-select output signal from
PAD B. PB0–PB7 can provide CS0–CS7, respectively. Each of the signals CS0–CS3 is
comprised of four product terms.Thus, up to four ANDed expressions can be ORed
while deriving any of these signals. Each of the signals CS4–CS7 is comprised of two
product terms. Thus, up to two ANDed expressions can be ORed while deriving any of
these signals.
Port B in 16-Bit Non-Multiplexed Address/Data Mode (ZPSD30X)
In this mode, Port B becomes the high-order data bus byte of the chip. When reading an
internal high-order data bus byte location, the data is presented on Port B pins. When
writing to an internal high-order data bus byte location, data present on Port B is written to
that location. See Table 9.
Accessing the I/OPort Registers
Tables 6 and 7 show the offset values with the respect to the base address defined by the
CSIOPORT. They let the user access the corresponding registers.
Port C in All Modes
Each pin of Port C (shown in Figure 8) can be configured as an input to PAD A and PAD
B or output from PAD B. As inputs, the pins are named A16–A18. Although the pins are
given names of the high-order address bus, they can be used for any other address lines or
logic inputs to PAD A and PAD B. For example, A8–A10 can also be connected to those
pins, improving the boundaries of CS0–CS7 resolution to 256 bytes. As inputs, they can be
individually configured to be logic or address inputs. A logic input uses the PAD only for
Boolean equations that are implemented in any or all of the CS0–CS10 PAD B outputs.
Port C addresses can be programmed to latch the inputs by the trailing edge ALE or to be
transparent.
Alternately, PC0–PC2 can become CS8–CS10 outputs, respectively, providing the user with
more external chip-select PAD outputs. Each of the signals CS8–CS10 is comprised of one
product term.
ALE/AS and A0–A15 in Non-Multiplexed Modes (ZPSD3X2/3X3/3X4R)
In non-multiplexed modes, A0–A15 are address inputs only and can become transparent
(CLOT = 0) or ALE dependent (CLOT = 1). In transparent mode, the ALE/AS pin can be
used as an additional logic input to the PADs. The non-multiplexed ALE dependent mode is
useful in applications for which the host processor has a multiplex address/data bus and
AD0/A0–AD7/A7 are not multiplexed with A0–A7 but rather are multiplexed with other
address lines. In these applications, Port A serves as a data bus and each of its pins can be
directly connected to the corresponding host’s multiplexed pin, where that data bit is
expected. (See Table 8.)
Port Functions
(Cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZPSD312V | Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,4位頁寄存器,19個可編程I/O,通用PLD有16個輸入) |
| ZPSD314R | Programmable Peripherals , ZPSD Power Consumption Calculations(可編程邏輯,零功耗，無SRAM,19個可編程I/O,通用PLD有16個輸入) |
| ZPSD314RV | Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，無SRAM,19個可編程I/O,通用PLD有16個輸入) |
| ZPSD301 | Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個可編程I/O,通用PLD有12個輸入) |
| ZPSD302 | Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個可編程I/O,通用PLD有16個輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD311 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PSD3XX/ZPSD3XX FAMILY LOW COST MICROCONTROLLER PERIPHERALS |
| ZPSD311-15J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD311-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD311-15LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD311-15LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。