參數(shù)資料
型號(hào)： ZPSD301V
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有12個(gè)輸入）
文件頁(yè)數(shù)： 42/90頁(yè)
文件大?。?/td> 491K
代理商： ZPSD301V
ZPSD3XX Famly
3-42
NOTES:
39. ADi = any address line.
40. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through Port C (CS8–CS10).
41. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or
R/W, transparent PC0–PC2, ALE (or AS).
42. Control signals RD/E/DS or WR or R/W.
-15
-20
-25
CMiser
On =
Add
Turbo
Of =
Add
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
Track Mode Address
Propagation Delay:
CSADOUT1 Already True
50
60
60
0
0
ns
T23
Latched Address Outputs,
Port A
50
60
60
0
0
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes True
During ALE or AS
T23A
70
80
90
0
20
ns
Track Mode Trailing Edge of
ALE or AS to Address High-Z
T24
50
60
60
0
0
ns
T25
Track Mode Read Propagation
Delay
45
55
60
0
0
ns
T26
Track Mode Read Hold Time
10
70
10
70
10
70
0
0
ns
T27
Track Mode Write Cycle,
Data Propagation Delay
45
55
60
0
0
ns
Track Mode Write Cycle,
Write to Data Propagation Delay
T28
8
65
8
75
8
80
0
20
ns
Hold Time of Port A Valid
During Write CSOi Trailing Edge
T29
2
3
3
0
0
ns
T30
CSI Active to CSOi Active
9
70
9
80
9
90
0
0
ns
T31
CSI Inactive to CSOi Inactive
9
70
9
80
9
90
0
0
ns
T32
Direct PAD Input as Hold Time
0
0
0
0
0
ns
T33
R/W Active to E or DS Start
30
40
50
0
0
ns
T34
E or DS End to R/W
30
40
50
0
0
ns
T35
AS Inactive to E high
0
0
0
0
0
ns
T36
Address to Leading Edge
of Write
30
35
40
0
0
ns
AC Characteristics
(Cont.)
(ZPSDV Versions Only)
(3.0 V ± 10%)
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