參數(shù)資料
型號(hào): ZL50233/GDG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁(yè)數(shù): 4/38頁(yè)
文件大?。?/td> 547K
代理商: ZL50233/GDG
ZL50233
Data Sheet
12
Zarlink Semiconductor Inc.
2.0
Device Configuration
The ZL50233 architecture contains 4 echo cancellers divided into 2 groups. Each group has two echo cancellers
which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in
three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8.
2.1
Normal Configuration
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously.
Figure 6 - Normal Device Configuration (64 ms)
2.2
Back-to-Back Configuration
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 7. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo
cancellation is required.
Figure 7 - Back-to-Back Device Configuration (64 ms)
Rin
Rout
Sout
Sin
echo
path A
echo
path B
+
-
channel A
channel A
+
-
channel B
channel B
ECA
ECB
Adaptive
Filter (64 ms)
Adaptive
Filter (64 ms)
PORT1
PORT2
+
ECA
Sin
Sout
Rout
Rin
-
ECB
+
-
echo
path
Adaptive
Filter (64 ms)
Adaptive
Filter (64 ms)
PORT1
PORT2
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