參數(shù)資料
型號: ZL50233/GDG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁數(shù): 10/38頁
文件大?。?/td> 547K
代理商: ZL50233/GDG
ZL50233
Data Sheet
18
Zarlink Semiconductor Inc.
Figure 11 - Power Up Sequence Flow Diagram
6.5
Power management
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
for description.
The typical power consumption can be calculated with the following equation:
PC = 9 * Nb_of_groups + 3.6, in mW
where 0
≤ Nb_of_groups ≤ 2.
6.6
Call Initialization
To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting
the echo canceller in bypass mode for at least one frame (125
s) and then enabling adaptation.
Since the Narrow Band Detector is “ON” regardless of the functional state of Echo Canceller it is recommended that
the Echo cancellers are reset before any call progress tones are applied.
System Powerup
Delay 100
s
Reset Held Low
Reset High
MCLK Active
Delay 500
s
Reg. Reset
Software
Hardware
Reset Low
Delay 1000ns
Reset High
PWUP to “1”
Delay 250
s
PWUP to “0”
Delay 500
s
ECAN Ready
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