參數(shù)資料
型號: ZL50232GD
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件頁數(shù): 32/41頁
文件大?。?/td> 809K
代理商: ZL50232GD
ZL50232
Data Sheet
38
Zarlink Semiconductor Inc.
Interrupt FIFO Register
Power-up 00hex
R/W Address: 410hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRQ
0
I4I3I2
I1I0
Functional Description of Register Bits
IRQ
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register
is read. Logic Low indicates that no interrupt is pending and the FIFO is empty.
0
Unused bit. Always zero.
0
Unused bit. Always zero.
I<4:0>
I<4:0> binary code indicates the channel number at which a Tone Detector state change has
occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Test Register
Power-up 00hex
R/W Address: 411hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserve
Tirq
Functional Description of Register Bits
Reserve
Reserved bits. Must always be set to zero for normal operation.
Tirq
Test IRQ: Useful for the application engineer to verify the interrupt service routine. When high,
any change to MTDBI and MTDAI bits of the Main Control Register will cause an interrupt and its
corresponding channel number will be available from the Interrupt FIFO Register. When low,
normal operation is selected.
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