參數(shù)資料
型號(hào): ZL50232GD
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件頁(yè)數(shù): 21/41頁(yè)
文件大小: 809K
代理商: ZL50232GD
ZL50232
Data Sheet
28
Zarlink Semiconductor Inc.
Power-up
00hex
ECA: Status Register
Read Address:
02hex + Base Address
ECB: Status Register
Read Address:
22hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserve
TD
DTDet
Reserve
TDG
NB
Functional Description of Register Bits
Reserve
Reserved bit
TD
Logic high indicates the presence of a 2100Hz tone
DTDet
Logic high indicates the presence of a double-talk condition
Reserve
Reserved bit
Reserve
Reserved bit
Reserve
Reserved bit
TDG
Tone detection status bit gated with the AutoTD bit. (Control Register 2)
Logic high indicates that AutoTD has been enabled and the tone detector has detected
the presence of a 2100Hz tone.
NB
Logic high indicates the presence of a narrow-band signal on Rin
Power-up
00hex
ECA: Flat Delay Register (FD)
R/W Address:
04hex + Base Address
ECB: Flat Delay Register (FD)
R/W Address:
24hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Power-up
00hex
ECA: Decay Step Number Register (NS)
R/W Address:
07hex + Base Address
ECB: Decay Step Number Register (NS)
R/W Address:
27hex+ Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NS7
NS6
NS5
NS4
NS3
NS2
NS1
NS0
Power-up
04hex
ECA: Decay Step Size Control Register (SSC)
R/W Address:
06hex + Base Address
ECB: Decay Step Size Control Register (SSC)
R/W Address:
26hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
SSC2
SSC1
SSC0
Note: Bits marked with “0” are reserved bits and should be written “0”
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