參數(shù)資料
型號(hào): ZL50232GD
廠商: ZARLINK SEMICONDUCTOR INC
元件分類(lèi): 數(shù)字傳輸電路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, LBGA-208
文件頁(yè)數(shù): 13/41頁(yè)
文件大?。?/td> 809K
代理商: ZL50232GD
ZL50232
Data Sheet
20
Zarlink Semiconductor Inc.
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS.
7.2
Instruction Register
In accordance with the IEEE 1149.1 standard, the ZL50232 uses public instructions. The JTAG Interface contains a
3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to
select the test data register that will operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register scanning.
7.3
Test Data Registers
As specified in IEEE 1149.1, the ZL50232 JTAG Interface contains three test data registers:
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around
the boundary of the ZL50232 core logic.
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
.
Typical figures are at 25
°C and are for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
1
I/O Supply Voltage (VDD1)VDD_IO
-0.5
5.0
V
2
Core Supply Voltage (VDD2)VDD_CORE
-0.5
2.5
V
3
Input Voltage
VI3
VSS - 0.5
VDD1+0.5
V
4
Input Voltage on any 5 V Tolerant I/O pins
VI5
VSS - 0.3
7.0
V
5
Continuous Current at digital outputs
Io
20
mA
6
Package power dissipation
PD
2W
7
Storage temperature
TS
-55
150
°C
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated
Characteristics
Sym.
Min,
Typ.
Max.
Units
1
Operating Temperature
TOP
-40
+85
°C
2
I/O Supply Voltage (VDD_IO)VDD1
3.0
3.3
3.6
V
3
Core Supply Voltage (VDD_CORE)VDD2
1.6
1.8
2.0
V
4
Input High Voltage on 3.3 V tolerant I/O
VIH3
0.7VDD1
VDD1
V
5
Input High Voltage on 5 V tolerant I/O pins
VIH5
0.7VDD1
5.5
V
6
Input Low Voltage
VIL
0.3VDD1
V
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