參數(shù)資料
型號: ZL50116GAG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: 32, 64 and 128 Channel CESoP Processors
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA324
封裝: 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034, BGA-324
文件頁數(shù): 65/95頁
文件大?。?/td> 1157K
代理商: ZL50116GAG
ZL50115/16/17/18/19/20
Data Sheet
65
Zarlink Semiconductor Inc.
Figure 24 - Jitter Transfer Function - Detail
10.0 Memory Map and Register Definitions
All memory map and register definitions are included in the ZL50115/16/17/18/19/20 Programmers Model
document.
11.0 DC Characteristics
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage
measurements are with respect to ground (V
SS
) unless otherwise stated.
* The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to
observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply current is available. To be
safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
I/O Supply Voltage
V
DD_IO
V
DD_CORE
V
DD_PLL
V
I
V
I_5V
I
IN
I
O
PD
-0.5
5.0
V
Core Supply Voltage
-0.5
2.5
V
PLL Supply Voltage
-0.5
2.5
V
Input Voltage
-0.5
V
DD
+ 0.5
7.0
V
Input Voltage (5 V tolerant inputs)
-0.5
V
Continuous current at digital inputs
-
±
10
mA
Continuous current at digital outputs
-
±
15
mA
Package power dissipation
-
2.38
W
Storage Temperature
TS
-55
+125
°
C
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相關(guān)代理商/技術(shù)參數(shù)
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