參數資料
型號： ZL50116GAG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網絡
英文描述： 32, 64 and 128 Channel CESoP Processors
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA324
封裝： 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034, BGA-324
文件頁數： 34/95頁
文件大?。?/td> 1157K
代理商： ZL50116GAG
ZL50115/16/17/18/19/20
Data Sheet
34
Zarlink Semiconductor Inc.
MII Port 1 (ZL50118/19/20 only)
Signal
I/O
Package Balls
Description
M1_LINKUP_LED
O
C17
LED drive for MAC 1 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
M1_ACTIVE_LED
O
B15
LED drive for MAC 1 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M1_RXCLK
I U
C4
MII only - Receive Clock.
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
M1_COL
I D
C5
Collision Detection. This signal is
independent of M1_TXCLK and
M1_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
M1_RXD[3:0]
I U
[3]
[2]
E1
D3
[1]
[0]
D1
D2
Receive Data. Clocked on rising edge of
M1_RXCLK.
M1_RXDV
I D
D5
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M1_RXCLK.
It is asserted when valid data is on the
M1_RXD bus.
M1_RXER
I D
E4
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M1_RXDV is asserted. Can be used
in conjunction with M1_RXD when
M1_RXDV signal is de-asserted to indicate
a False Carrier.
M1_CRS
I D
F2
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
M1_TXCLK
I U
E3
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
M1_TXD[3:0]
O
[3]
[2]
C1
B1
[1]
[0]
B5
B4
Transmit Data. Clocked on rising edge of
M1_TXCLK.
M1_TXEN
O
A2
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M1_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
Table 9 - MII Port 1 Interface Package Ball Definition
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相關代理商/技術參數
參數描述
ZL50116GAG2 制造商:Microsemi Corporation 功能描述:PB FREE 2 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 64CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 64CH 324PBGA
ZL50117 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors
ZL50117_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors
ZL50117GAG 制造商:Microsemi Corporation 功能描述:4 TDM + 1 ETHERNET - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 324PBGA
ZL50117GAG2 制造商:Microsemi Corporation 功能描述:PB FREE 4 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:PB FREE 4TDM PLUS 1 ETHERNET 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 324PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 324PBGA
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