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參數(shù)資料
| 型號(hào)： | ZL30406 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | SONET/SDH Clock Multiplier PLL |
| 中文描述： | SONET / SDH的時(shí)鐘倍頻鎖相環(huán) |
| 文件頁數(shù)： | 6/21頁 |
| 文件大小： | 307K |
| 代理商： | ZL30406 |
ZL30406
Data Sheet
6
Zarlink Semiconductor Inc.
1.4 Output Interface Circuit
The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at
77.76 MHz, one programmable CML differential clock (19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz) controlled
with FS1-2 pins and a single-ended 19.44 MHz output clock. This block provides also a 19.44 MHz feedback clock
that closes PLL loop. Each output clock can be enabled or disabled individually with the associated Output Enable
pin.
To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be
disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations.
The output clock frequency of the OC-CLKo CML differential output clock is selected with FS1-2 pins as shown in
the following table.
Output Clocks
Output Enable Pins
C77oP/N-A
C77oEN-A
C77oP/N-B
C77oEN-B
C77oP/N-C
C77oEN-C
C77oP/N-D
C77oEN-D
OC-CLKoP/N
OC-CLKoEN
C19o
C19oEN
Table 1 - Output Enable Control
FS2
FS1
OC-CLKo
Frequency
0
0
19.44 MHz
0
1
38.88 MHz
1
0
77.76 MHz
1
1
155.52 MHz
Table 2 - OC-CLKo Clock Frequency Selection
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| ZL30406_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
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