參數(shù)資料
型號: ZL30406
廠商: Zarlink Semiconductor Inc.
英文描述: SONET/SDH Clock Multiplier PLL
中文描述: SONET / SDH的時鐘倍頻鎖相環(huán)
文件頁數(shù): 3/21頁
文件大?。?/td> 307K
代理商: ZL30406
ZL30406
Data Sheet
3
Zarlink Semiconductor Inc.
12
OC-CLKoEN
SONET/SDH Clock Enable (CMOS Input).
If tied high this control pin enables
the OC-CLKoP/N differential driver. Pulling this input low disables the output
clock without deactivating differential drivers.
13
C77oEN-A
C77 Clock Output Enable A (CMOS Input).
If tied high this control pin
enables the C77oP/N-A output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
14
C77oEN-B
C77 Clock Output Enable B (CMOS Input).
If tied high this control pin
enables the C77oP/N-B output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
15
C77oEN-C
C77 Clock Output Enable C (CMOS Input).
If tied high this control pin
enables the C77oP/N-C output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
16
C77oEN-D
C77 Clock Output Enable D (CMOS Input).
If tied high this control pin
enables the C77oP/N-D output clock. Pulling this input low disables the output
clock without deactivating differential drivers.
17
GND
Ground.
0 volt
18
VDD
Positive Digital Power Supply.
+3.3 V ±10%
19
NC
No internal bonding Connection. Leave unconnected.
20
NC
No internal bonding Connection. Leave unconnected.
21
NC
No internal bonding Connection. Leave unconnected.
22
VDD
Positive Digital Power Supply.
+3.3 V ±10%
23
IC
Internal Connection.
Connect this pin to Ground (GND).
24
25
FS2
FS1
Frequency Select 2-1 (CMOS Input)
. These inputs program the clock
frequency on the OC-CLKo output. The possible output frequencies are
19.44 MHz (00), 38.88 MHz (01), 77.76 MHz (10), 155.52 MHz (11).
26
C19oEN
C19o Output Enable (CMOS Input).
If tied high this control pin enables the
C19o output clock. Pulling this pin low forces output driver into a high
impedance state.
27
GND
Ground.
0 volt
28
C19i
C19 Reference Input (CMOS Input).
This pin is a single-ended input reference
source used for synchronization. This pin accepts 19.44 MHz.
29
VDD
Positive Digital Power Supply.
+3.3 V ±10%
30
GND
Ground.
0 volt
31
NC
No internal bonding Connection. Leave unconnected.
32
GND
Ground.
0 volt.
33
GND
Ground.
0 volt
34
VDD
Positive Digital Power Supply.
+3.3 V ±10%
35
C19o
C19 Clock Output (CMOS Output)
. This pin provides a single-ended CMOS
clock at 19.44 MHz.
Pin Description Table (continued)
Pin #
Name
Description
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