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參數(shù)資料
| 型號(hào)： | ZL30108 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Network Interface DPLL |
| 中文描述： | 網(wǎng)絡(luò)接口數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 531K |
| 代理商： | ZL30108 |
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ZL30108
Data Sheet
7
Zarlink Semiconductor Inc.
2.0 Functional Description
The ZL30108 is a SONET/SDH Network Interface DPLL, providing timing (clock) and synchronization (frame)
signals to SONET/SDH network interface cards. Figure 1 is a functional block diagram which is described in the
following sections.
2.1 Reference Select Multiplexer (MUX)
The ZL30108 accepts two simultaneous reference input signals and operates on their rising edges. One of two, the
primary reference (REF0) or the secondary reference (REF1) signal is selected as input to the TIE Corrector Circuit
based on the Reference Selection (REF_SEL) input.
2.2 Reference Monitor
The input references are monitored by two independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
Reference Frequency Detector (RFD)
: This detector determines whether the frequency of the reference
clock is 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz 8.192 MHz, 16.384 MHz or 19.44 MHz and provides this
information to the various monitor circuits and the phase detector circuit of the DPLL.
Precise Frequency Monitor (PFM)
: This circuit determines whether the frequency of the reference clock
is within the applicable accuracy range defined by the OOR_SEL pin, see Figure 5, Figure 6 and Table 2.
It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.
Coarse Frequency Monitor (CFM)
: This circuit monitors the reference over intervals of approximately
30 μs to quickly detect large frequency changes.
Single Cycle Monitor (SCM)
: This detector checks the period of a single clock cycle to detect large
phase hits or the complete loss of the clock.
Figure 3 - Reference Monitor Circuit
Reference Frequency
Detector
Single Cycle
Monitor
Precise Frequency
Monitor
Coarse Frequency
Monitor
dis/requalify
timer
REF0 /
REF1
OR
OR
REF_DIS= reference disrupted (internal signal)
Mode select
state machine
REF_DIS
REF_FAIL0 /
REF_FAIL1
HOLDOVER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30108LDE1 | SONET/SDH Network Interface DPLL |
| ZL30109QDG1 | DS1/E1 System Synchronizer with |
| ZL30109 | DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30109QDG | DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30110 | Telecom Rate Conversion DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30108_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Network Interface DPLL |
| ZL30108LDA | 制造商:Microsemi Corporation 功能描述:SONET/SDH NETWORK INTRFC DPLL 32QFN - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH NETWORK INTRFC DPLL 32QFN - Rail/Tube |
| ZL30108LDE1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Network Interface DPLL |
| ZL30108LDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE SONET/SDH NETWORK INTERFACE DPLL - Trays 制造商:Microsemi Corporation 功能描述:PBFREE SONET&SDH NETWORK I/F DPLL TRAY 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DPLL SONET/SDH 32QFN 制造商:Microsemi Corporation 功能描述:IC DPLL SONET/SDH 32QFN |
| ZL30109 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with 19.44 MHz Output |
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