參數(shù)資料
型號(hào): ZL30108
廠商: Zarlink Semiconductor Inc.
英文描述: Network Interface DPLL
中文描述: 網(wǎng)絡(luò)接口數(shù)字鎖相環(huán)
文件頁(yè)數(shù): 18/28頁(yè)
文件大?。?/td> 531K
代理商: ZL30108
ZL30108
Data Sheet
18
Zarlink Semiconductor Inc.
5.2 Master Clock
The ZL30108 can use either a clock or crystal as the master timing source. Zarlink Application Note ZLAN-68 lists a
number of applicable oscillators and crystals that can be used with the ZL30108.
5.2.1 Clock Oscillator
When selecting a Clock Oscillator, numerous parameters must be considered. These includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30108 and the OSCo
output should be left open as shown in Figure 11.
Figure 11 - Clock Oscillator Circuit
1
Frequency
20 MHz
2
Tolerance
As required
3
Rise & Fall Time
<10 ns
4
Duty Cycle
40% to 60%
Table 5 - Typical Clock Oscillator Specification
+3.3 V
20 MHz OUT
GND
0.1 μF
+3.3 V
OSCo
ZL30108
OSCi
No Connection
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