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參數(shù)資料
| 型號： | ZL30108LDE1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH Network Interface DPLL |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, MO-220, QFN-32 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 293K |
| 代理商： | ZL30108LDE1 |
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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Supports output wander and jitter generation
specifications for GR-253-CORE OC-3 and G.813
STM-1 SONET/SDH interfaces
Accepts two input references and synchronizes to
any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
Provides a 19.44 MHz (SONET/SDH) clock output
Provides an 8 kHz framing pulse and a 2 kHz
multi-frame pulse
Provides automatic entry into Holdover and return
from Holdover
Hitless reference switching between any
combination of valid input reference frequencies
Provides lock and accurate reference fail
indication
Loop filter bandwidth of 29 Hz or 14 Hz
Less than 24 ps
rms
intrinsic jitter on the 19.44 MHz
output clock, compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications
Less than 0.5 ns
pp
intrinsic jitter on output frame
pulses
External master clock source: clock oscillator or
crystal
Simple hardware control interface
Applications
Line card synchronization for SONET/SDH
systems
Description
The ZL30108 SONET/SDH network interface digital
phase-locked loop (DPLL) provides timing and
synchronization for SONET/SDH network interface
cards.
The ZL30108 generates a SONET/SDH clock and
framing signals that are phase locked to one of two
backplane or network references. It helps ensure
system reliability by monitoring its references for
frequency accuracy and stability and by maintaining
tight phase alignment between the input reference
clock and clock outputs.
The ZL30108 output clock’s wander and jitter
generation are compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications.
March 2006
Ordering Information
ZL30108LDA
ZL30108LDE1
32 Pin QFN
32 Pin QFN*
*Pb Free Matte Tin
-40
°
C to +85
°
C
Tubes
Tubes, Bake & Drypack
ZL30108
SONET/SDH
Network Interface DPLL
Data Sheet
Figure 1 - Functional Block Diagram
Reference
Monitor
Mode
Control
Virtual
Reference
TIE
Corrector
Enable
State Machine
Frequency
Select
TIE
Corrector
Circuit
MODE_SEL
REF1
RST
REF_SEL
TIE_CLR
OSCo
OSCi
Master Clock
REF0
LOCK
REF_FAIL0
REF_FAIL1
DPLL
MUX
Frequency
Synthesizer
F8ko
F2ko
C19o
OOR_SEL
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PDF描述 |
|---|---|
| ZL30109QDG1 | DS1/E1 System Synchronizer with |
| ZL30109 | DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30109QDG | DS1/E1 System Synchronizer with 19.44 MHz Output |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30108LDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE SONET/SDH NETWORK INTERFACE DPLL - Trays 制造商:Microsemi Corporation 功能描述:PBFREE SONET&SDH NETWORK I/F DPLL TRAY 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DPLL SONET/SDH 32QFN 制造商:Microsemi Corporation 功能描述:IC DPLL SONET/SDH 32QFN |
| ZL30109 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30109_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with |
| ZL30109QDG | 制造商:Microsemi Corporation 功能描述: |
| ZL30109QDG1 | 制造商:Microsemi Corporation 功能描述:DS1/E1 System Synchronizer 64-Pin TQFP 制造商:Microsemi Corporation 功能描述:DS1/E1 SYS. SYNCH WITH 19.44MHZ 制造商:Microsemi Corporation 功能描述:DS1/E1 SYS SYNCHRONIZER 64TQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER DPLL 64TQFP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER DPLL 64TQFP |
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