參數(shù)資料
型號(hào)： ZL30101
廠商： Zarlink Semiconductor Inc.
英文描述： T1/E1 Stratum 3 System Synchronizer
中文描述： T1/E1的Stratum 3系統(tǒng)同步
文件頁(yè)數(shù)： 10/34頁(yè)
文件大小： 534K
代理商： ZL30101
ZL30101
Data Sheet
10
Zarlink Semiconductor Inc.
3.0 Functional Description
The ZL30101 is a DS1/E1 Stratum 3 System Synchronizer providing timing (clock) and synchronization (frame)
signals to interface circuits for DS1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block
diagram which is described in the following sections.
3.1 Reference Select Multiplexer (MUX)
The ZL30101 accepts two simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0) or the secondary reference (REF1) signal can be selected as input to the TIE
corrector circuit based on the reference selection (REF_SEL) input.
3.2 Reference Monitor
The input references are monitored by two independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
Reference Frequency Detector (RFD)
: This detector determines whether the frequency of the reference
clock is 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz and provides this information to the
various monitor circuits and the phase detector circuit of the DPLL.
Precise Frequency Monitor (PFM)
: This circuit determines whether the frequency of the reference clock
is within the applicable accuracy range of
±
12 ppm, see Figure 5. It will take the precise frequency monitor
up to 10 s to qualify or disqualify the input reference.
Coarse Frequency Monitor (CFM)
: This circuit monitors the reference frequency over intervals of
approximately 30
μ
s to quickly detect large frequency changes.
Single Cycle Monitor (SCM)
: This detector checks the period of a single clock cycle to detect large
phase hits or the complete loss of the clock.
59
IC
Internal Connection.
Connect this pin to ground.
60
IC
Internal Connection.
Connect this pin to ground.
61
V
DD
NC
Positive Supply Voltage.
+3.3 V
DC
nominal.
No internal bonding Connection.
Leave unconnected.
62
63
TIE_CLR
TIE Corrector Circuit Reset (Input).
A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a realignment of the input phase with the output
phase.
64
BW_SEL
Filter Bandwidth Selection (Input).
This pin selects the bandwidth of the DPLL loop
filter, see Table 1 on page 17. Set continuously high to track jitter on the input reference
closely or temporarily high to allow the ZL30101 to quickly lock to the input reference.
Pin Description (continued)
Pin #
Name
Description
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ZL30101_06 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 3 System Synchronizer
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ZL30102 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
ZL30102_05 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
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